OBJECTIVE: The objective of this work is to develop the initial ability to test the functionality automatically of all the die on a wafer before it is diced to find the working die and then to mount the"known-good"die into a larger circuit in such a way that repair to the functionality of the whole can be accomplished by replacing the part, not the whole. Such shrinkage of the line replaceable units will make the costs of building complex system functionality in immature digital technologies more affordable. Substantial innovation on packaging technology is required to deliver success on this topic as reworkable cryogenic epoxies are unknown and automated testing protocols at the expected 10's of GHz clock speeds are very immature, even at room temperature. Existing 6 probe RF commercial testing stations that can deliver signals at the clock frequency currently heat the active device to>6K, unacceptable for the required<4.5K 200 probe testing. DESCRIPTION: When a digital device technology is immature, as is the case today for both the advanced semiconductors and the superconductors, it is desirable to be able to assemble a complex circuit out of smaller die that have been individually tested and are known before assembly to be fully operational. These"known good die"must therefore be tested without permanently attaching them to a test circuit. Instead a method of bonding that can be reversed without subjecting the die to a too elevated temperature or chemical components that can degrade the circuit functionality must be located. Reworkable epoxy that can be etched away in a process similar to that used for MEMs sacrificial layers may be a good method of achieving that goal. Moreover, it is desirable to have a method of doing automated testing of stepper reticle areas and eventually whole wafers of the die. Having such a technique eliminates the costs of technician time dicing and packaging non-functional die, while the number of die actually tested increases, thereby facilitating statistical process control. The proposal should state the planned approach to accomplishing both these goals and the expected division of labor between bonding and testing subefforts. PHASE I: Focus on the superconducting case which sets a maximum processing temperature for both assembly and disassembly of 125C and establishes the exposed materials as fine grained Nb, its oxides, Al, Mo, amorphous Al2O3, SiO2 and Si3N4 and the substrate as Si coated with SiO2. Demonstrate as a proof of concept that a reworkable epoxy (or alternative bonding method) can produce low electrical resistance bonds which are mechanically robust under ultrasonic vibration as set, withstand thermal cycling to 4K, and can be fully removed when processed to release. Ideally the bonding method will also help remove heat from the face of the active die at 4K. Elaborate method of extending the approach from single die to arrays of such die on a reticle area/full wafer. Alternatively, elaborate a method of performing at speed (>20 GHz) and temperature (<4.5K) testing of repeated die structures on common substrate and define how reconfigurable wiring connections to room temperature signal and current generators will be accomplished. PHASE II: Iterate the bonding method, develop and demonstrate the whole wafer bonding concept, and culminate work with a demonstration of both a 4 die MCM manufacture and successful automated test at clock speeds above 20 GHz of at least 2 different die while still in whole wafer/reticle form. PHASE III: Become the bonding method of choice for the digital and mixed signal low temperature device community. PRIVATE SECTOR COMMERCIAL POTENTIAL/DUAL-USE APPLICATIONS: The government supercomputer market is less than 5% of the whole market for such machines; multiple user base stations renting BW may be a viable business model. Thus the applicability of this effort to these 2 that the technology developed will have dual use applications.