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Radiation Hardened By Design Structured ASICs for Reliable Digital Components
Title: Chief Scientist
Phone: (505) 507-0542
Title: Director Business Operati
Phone: (505) 294-1962
The Phase II effort will fully develop and realize a cost-effective, practically-oriented means to design and deliver radiation hardened digital electronic components capable of reliable operation in MDA and other DoD space and interceptor environments. Micro-RDC will accomplish this by working closely with ViASIC to integrate both new and existing radiation design hardening techniques into their VPGA fabric. We will also develop a number of specific digital functions that cannot be easily or efficiently instantiated within the existing logic fabric. These macros will include cache SRAM blocks, via-programmable ROM blocks, high-speed LVDS transceiver and SERDES IO capability, and on-chip phase locked and/or delay locked loops. The via programmable general IO capability will also be extended for the current VPGA to additionally include internal signal and power IO for bump bonding in high pad count applications. As the program progresses, additional high level macro blocks may later be identified and implemented. The Phase II effort will focus on implementing the VPGA and associated macros in the 90 nm IBM CMOS 9 LP technology. The results of the Phase II effort will be a realized mask set of the VPGA that can be used for product targeting.
* Information listed above is at the time of submission. *