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Realization of Mulitlayer High Temperature Capacitors with New Dielectric Materials and Novel Thermal Spray Deposition Route

Award Information
Agency: Department of Energy
Branch: N/A
Contract: DE-FG02-13ER86567
Agency Tracking Number: 76406
Amount: $149,993.00
Phase: Phase I
Program: STTR
Solicitation Topic Code: 01a
Solicitation Number: DE-FOA-0000801
Solicitation Year: 2013
Award Year: 2013
Award Start Date (Proposal Award Date): 2013-06-10
Award End Date (Contract End Date): N/A
Small Business Information
1917 W 234th Street
Torrance, CA 90501-5532
United States
DUNS: 964921345
HUBZone Owned: No
Woman Owned: Yes
Socially and Economically Disadvantaged: No
Principal Investigator
 Clive Randall
 (814) 863-1328
Business Contact
 Rashmi Dixit
Title: Dr.
Phone: (424) 263-4002
Research Institution
 The Pennsylvania State University
N-221 Millennium Science Complex
University Park, PA 16802-
United States

 () -
 Nonprofit College or University

The main focus of this STTR is to design, develop, and evaluate high temperature capacitors using novel thermal spray coating processes, which will allow the devices to meet the performance requirements. Multilayer coating architecture will be adopted and the electrodes and dielectric material selections will be screened in Phase I to note material compatibility and high temperature performance. The Center for Dielectrics Studies, CDS at Penn State University, over the last 3-6 years, has discovered a number of important new dielectric materials for co- firing and multilayer assembly. These materials have shown a wide variety of polarization phenomena and provide different opportunities for high temperature dielectrics, some of which have already gone through pilot line testing, and have been introduced as potential new multilayer ceramic capacitors for high temperature applications. There is, very good reliability performance at 150 oC, but so far there are still issues in long time performance at 200 and 250 oC, and the second- and third-generation high temperature capacitors require a major innovation in approach and in materials to improve the mean time to failure performance at high field and high temperatures. Capacitor technology in general, requires characterization tools and theories to improve the optimization and life-testing for high temperature operation. We are outlining a novel processing strategy with a variety of high performance dielectric oxides that could provide a revolutionary approach to obtain high temperature capacitors independent of the multilayer tape-casting route, but with a cost effective deposition technique that is scalable for high volume cost effect production. The Phase I will consider the deposition of selected dielectrics with single layers and also show the possibility of multilayer production with the shadow mask approach. Data from phase I on selected dielectrics will then be taken to focus efforts on prototyped larger capacitors with more rigor including reliability studies in phase II. The overall capacitor architecture will be designed using the novel thermal spray coating process and is based on multilayer coating structure. The form factor will be realized using a novel shadow mask technology to provide unique microstructures and processing routes that permit low ESR and ESL, and high temperature reliability. The thermal spray method allows low temperature deposition of both the dielectric material and the electrode material in a sequential and rapid processing route that avoids the complexities of binder removal, sintering etc. Commercial Applications and Other Benefits: Application areas for this type of capacitor technologies can be switch mode power supplies, supplies, linear accelerator capacitors, ac-dc invertors, pulse power, energy storage, electric armor etc. The attraction of this proposed fabrication approach would be the ability to fabricated larger high capacitance devices, where the convention processing problems such as binder removal, electrode interactions in electrode ceramic interfaces and co-firing transient stresses limit larger device fabrication.

* Information listed above is at the time of submission. *

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