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System Engineer Toolset for Fault Tolerant Design
Phone: (505) 255-8611
This SBIR will explore and develop new automated methods for dynamic fault tolerance in defense electronic systems. The research will investigate using the software of digital signal processor operating systems to pro-actively map defective operations to remaining processors. In the past, fault tolerance has relied on passive redundancy to extend operating life. With software, a simple re-start, or a shift to non-corrupted memory and processor may be all that is needed. In Phase I, research will be based in ongoing Rapid Prototyping of Application Specific Signal Processors (RASSP) development. The RASSP design tools and project scientists will be used to develop the algorithms that provide scalable, heterogeneous computing systems with a new breed of fault tolerance based on dynamic reconfiguration of resources. In Phase II the system will be developed using networked UNIX computers. In Phase II the technology will be tried aboard a US Navy combat ship.
* Information listed above is at the time of submission. *