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System Engineer Toolset for Fault Tolerant Design

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: N/A
Agency Tracking Number: 32513
Amount: $98,902.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Solicitation Year: N/A
Award Year: 1996
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
6022 Constitution Ave. N.E.
Albuquerque, NM 87110
United States
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Kenneth Blemel
 (505) 255-8611
Business Contact
Phone: () -
Research Institution

This SBIR will explore and develop new automated methods for dynamic fault tolerance in defense electronic systems. The research will investigate using the software of digital signal processor operating systems to pro-actively map defective operations to remaining processors. In the past, fault tolerance has relied on passive redundancy to extend operating life. With software, a simple re-start, or a shift to non-corrupted memory and processor may be all that is needed. In Phase I, research will be based in ongoing Rapid Prototyping of Application Specific Signal Processors (RASSP) development. The RASSP design tools and project scientists will be used to develop the algorithms that provide scalable, heterogeneous computing systems with a new breed of fault tolerance based on dynamic reconfiguration of resources. In Phase II the system will be developed using networked UNIX computers. In Phase II the technology will be tried aboard a US Navy combat ship.

* Information listed above is at the time of submission. *

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