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Ultrafast Physical Random Number Generation Using Chaos

Award Information
Agency: Department of Defense
Branch: Army
Contract: W31P4Q-16-C-0008
Agency Tracking Number: A2-6024
Amount: $572,566.00
Phase: Phase II
Program: STTR
Solicitation Topic Code: A14A-T002
Solicitation Number: 2014.0
Solicitation Year: 2014
Award Year: 2016
Award Start Date (Proposal Award Date): 2015-12-17
Award End Date (Contract End Date): 2017-12-17
Small Business Information
4035 Chris Drive
Huntsville, AL 35802
United States
DUNS: 122515708
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Dan Hahs
 (256) 319-6016
Business Contact
 Kenneth Lones
Phone: (256) 319-6019
Research Institution
 Auburn University
 Jennifer Welch
126 Ingram Hall \N
Auburn, AL 36849-5102
United States

 (334) 844-5953
 Nonprofit College or University

Random numbers are essential for a growing number of modern applications. As computer speed and communications bandwidth have increased the potential for practical streaming cipher and large-scale Monte Carlo simulations have become technologically feasible. For these and other applications, ultrafast random number generators are essential. This is intuitively clear. Additionally, however, the ideality of true random numbers must also be imposed for the sake of key security and stochastic distribution fidelity. Pseudorandom numbers are insufficient. Interestingly, these stringent specifications can be met through the deterministic phenomenon of dynamical chaos. Chaotic physical systems, based on the concept of exactly-solvable chaos, naturally produce symbol sequences that are provably stochastically ideal. Thus far, in a Phase I STTR, we have demonstrated, at a proof-of-principle level, that the concept is soundly based and that suitable electronic circuits for the application are realizable. In this Phase II proposal, we present a plan to mature the true random number generator in terms of stochastic fidelity, data and entropy rates, performance stability, environmental robustness and reproducibility, culminating in an Application Specific Integrated Circuit (ASIC) that will be subjected to standard tests for randomness and other design specifications. Test results, operational theory and user data will be documented.

* Information listed above is at the time of submission. *

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