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Analog Co-Processors for Complex System Simulation and Design

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: W31P4Q-16-C-0064
Agency Tracking Number: D15C-002-0019
Amount: $154,047.00
Phase: Phase I
Program: STTR
Solicitation Topic Code: ST15C-002
Solicitation Number: 2015.0
Solicitation Year: 2015
Award Year: 2016
Award Start Date (Proposal Award Date): 2016-03-21
Award End Date (Contract End Date): 2017-01-20
Small Business Information
P.O. Box 2607
Winnetka, CA 91396
United States
DUNS: 082191198
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Jim Friel
 (571) 255-4003
Business Contact
 Dr. Greg Fetzer
Phone: (303) 651-6756
Research Institution
 University of Virginia
 Robert R Merhige
P.O. Box 400195 \N
Charlottesville, VA 22904-4195
United States

 (434) 924-4270
 Nonprofit College or University

It has long been known that analog computers can be faster and more power efficient than digital processors by many orders of magnitude. Until the 1970s analog computers were the dominant controllers in most industrial and military applications. Even today digital processors are still slower and more power consumptive than analog, but offer much more flexibility (programmability) and precision. The fist hybrid approach to combine the best of both technologies dates to 1971 where a hybrid analog/digital design solved the heat equation ten times fast than the comparable digital computer but the demonstration used discrete components and was not practical for large problems. In 2006, Cowan used essentially the same architecture but in VLSI to solve the same heat equation 100x faster and with 1% of the power of the comparable digital processor and was shown to be scalable. We propose to extend Cowans work to second order in time and incorporate the latest advances in programmability from the FPAA community to design a true programmable, hybrid processor capable of direct solution of systems of non-linear PDEs and verify via simulation the same 100x, 1% performance of Cowan. Fabrication of a VLSI chip will be the focus of Phase II.

* Information listed above is at the time of submission. *

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