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A collaboration to develop a commercialization path or a Photonic Memory Controller Module (P-MCM)

Award Information
Agency: Department of Energy
Branch: N/A
Contract: DE-SC0017085
Agency Tracking Number: 0000227430
Amount: $224,566.00
Phase: Phase I
Program: STTR
Solicitation Topic Code: 04a
Solicitation Number: DE-FOA-0001618
Solicitation Year: 2017
Award Year: 2017
Award Start Date (Proposal Award Date): 2017-02-21
Award End Date (Contract End Date): 2017-11-20
Small Business Information
673 North Wilson Road
Columbus, OH 43204-1461
United States
DUNS: 079650683
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Schumacher Michael
 (614) 648-0113
Business Contact
 Spector Andy
Phone: (301) 395-7226
Research Institution
 Columbia University
116th Street & Broadway
New York, NY 10027
United States

 Nonprofit College or University

As computational density for high-performance computing and big-data services continues to scale, performance scalability of next generation computing systems is becoming increasingly constrained by limitations in memory access, power dissipation and chip packaging. The processor-memory communication bottleneck, a major challenge in current multicore processors due to limited pin-out and power budget, presents a detrimental scaling barrier to data-intensive computing. To address this issue, we assembled a consortium team of small businesses and leading researchers that includes experts from photonics processor-memory architecture, III/V photonic laser design/fabrication, silicon photonics design/fabrication, photonics packaging and assembly, and FPGA-based high performance memory controller IP development – to collaboratively develop a commercialization path for a photonic Memory Controller Module (P-MCM), targeted to meet the following specifications: (1) Provide optical interconnects between sever-class multiprocessor chip and multiple (> 10) high density stacked memory modules; (2) Target at the next-generation high density stacked memory modules, including High Bandwidth memory (HBM), Hybrid Memory Cube (HMC), and Wide I/O, etc.; (3) Power efficiency – not larger than 0.5 pJ/bit; (4) I/O bandwidth – 5 TB/s aggregate I/O rate for each memory module; (5) Network reconfigurability at nanosecond scale– optical switching fabric and fast tunable laser; (6) Wavelength division multiplexing (WDM) and optical multicast. During Phase I: (a) Columbia University will coordinate the working group and subgroups to provide the system architecture and specifications for each small business consortium team members. Columbia will develop high performance memory controller IPs and interfaces in FPGAs platform; (b) Freedom Photonics will develop the programmable, tunable laser using mature InP/GaAs processing; (c) Analog Photonics will develop the photonic transceiver and interconnect fabrics using silicon photonic processing through the American Institute for Manufacturing (AIM) Integrated Photonics multi-project wafer and assembly (MPWA) facilities; (d) PLC Connections will provide photonics packaging including passive optical packaging of the photonic transceiver and interconnect fabric chips, and provide a low-loss and robust optical coupling mechanism.

* Information listed above is at the time of submission. *

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