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Thickness Measurement Technology for Thin Films on Sapphire Substrate

Award Information
Agency: Department of Defense
Branch: Defense Microelectronics Activity
Contract: HQ072717P0026
Agency Tracking Number: E16B-001-0007
Amount: $149,965.16
Phase: Phase I
Program: STTR
Solicitation Topic Code: DMEA16B-001
Solicitation Number: 2016.0
Solicitation Year: 2016
Award Year: 2017
Award Start Date (Proposal Award Date): 2017-08-18
Award End Date (Contract End Date): 2018-03-15
Small Business Information
1046 New Holland Avenue
Lancaster, PA 17601
United States
DUNS: 126288336
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Nathan Van Velson
 R&D Engineer
 (717) 295-6822
Business Contact
 Mr. Frank Morales
Phone: (717) 295-6092
Research Institution
 Iowas State University
 Xinwei Wang
2010 Black Engineering Building Department of Mechanical Engineering, Iowa State University
Ames, IA 50011
United States

 (515) 294-2085
 Nonprofit college or university

Silicon-on-sapphire (SOS) integrated circuits are attracting attention due to their high speed performance and low power consumption. An important aspect of the SOS fabrication process that must be verified to maximize yield is the thickness of the thin films deposited on the sapphire substrate. However, due to the transparent nature of sapphire, current optical metrology tools are not applicable. Advanced Cooling Technologies, Inc. (ACT) proposes a Small Business Technology Transfer (STTR) Phase I program to develop and demonstrate an easy-to-use, non-contact and non-destructive, high resolution instrument for performing thin film and thin film stack thickness measurements for SOS devices. The proposed novel technique uses an alternative spectrographic technique to quickly and accurately determine thin film thicknesses with sub-nm accuracy. In the Phase I program, the feasibility of this technique will be proved through laboratory demonstration. In the Phase II program, the technique will be packaged into an instrument that can be integrated into an SOS wafer fabrication process.

* Information listed above is at the time of submission. *

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