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Micro-electronics Packaging, Thermal Management & Systems Integration


Proposals are solicited on more efficient means of integrating semiconductor components and devices into systems. The growth in chip density, coupled with the demand for high performance, small size, light weight, and affordable reliability has placed enormous pressure on interconnect technology and packaging at all levels. Innovations include (but not limited to) improved techniques for interconnect and packaging at the board level, packaging approaches for board components and passive components, techniques for board assembly, and applications of techniques to packaging and systems integration for optoelectronics and wireless systems. Memory continues to be a critical element in the full range of VLSI applications from big data to mobile applications to wearable devices. Recent trends, including process technology scaling limits, new memory applications, and evolving high-performance and low-power requirements, have driven the development of emerging memories, and their attendant packaging requirements.
Packaging, thermal management, and systems integration for sub-7nm CMOS, thin film/organic transistors, nanoscale III-V MOSFETs, 3D integrated circuits, silicon photonics; CMOS microfluidics, 3D flash memory, portable functional brain imagers, and biosensor arrays are of interest. Proposals that address packaging issues that involve power management circuits; wireless power transfer; energy harvester circuits; ultra-low voltage, low power circuits; neuromorphic circuits; advanced memory circuits, neural interface circuits; SoCs for mobile vision, sensing, and communications; micro-vacuum electronics; thin-film growth/epitaxy; novel IC films; ion implantation advanced RF circuit design and architectures (SOI, SiGe, GaAs); micro-valves and micro-turbines; and electrostatic discharge protection are also of interest. Higher current at lower voltage drives thermal management needs of electronic devices. Proposals that address novel packaging concepts such as graphene wrapper versus hermetic or plastic modules; passive and active heat sinks; nanowire patterning and processing; layer transfer (removing active IC and transferring to a different substrate (e.g. heat sink); through-silicon via for placement versus added capacitance; robust surface-mount PCB technology; flip chip versus wire bond through wafer vias; novel high thermal conductivity films on chip (e.g. SiC, graphene, borene); and novel hi-kappa fluids for cooling.
Proposals that involve or consider heat sinking from SOI (off-current reduction, logic standby current reduction); advanced electro-thermal circuit simulation packages beyond high frequency structural simulators (HFSS); energy harvesting devices such as ZnO; reduced harmonic loss at high power to meet FCC specifications; integrated device micro-cooling: ferroic magnetocaloric, electrocaloric, strain-induced cooling; micro-cooled FET and bipolar circuit boards; self-powered devices; advanced circuitry involving electronic duty cycle feedback control; nano-fans and piezo micro-blowers; and structured packaging design optimization system are of interest.

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