You are here

High-Speed Platform for Highly parallel STM lithography and hierarchical Assembly

Award Information
Agency: Department of Energy
Branch: N/A
Contract: DE-SC0018527
Agency Tracking Number: 0000234858
Amount: $149,795.00
Phase: Phase I
Program: STTR
Solicitation Topic Code: 17e
Solicitation Number: DE-FOA-0001770
Timeline
Solicitation Year: 2018
Award Year: 2018
Award Start Date (Proposal Award Date): 2018-04-09
Award End Date (Contract End Date): 2019-04-08
Small Business Information
1301 North Plano Road
Richardson, TX 75081-2426
United States
DUNS: 796537269
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 James Owen
 (972) 792-1632
 jowen@zyvexlabs.com
Business Contact
 John Randall
Phone: (972) 792-1648
Email: jrandall@zyvexlabs.com
Research Institution
 University of Texas at Dallas
 S.O. R Moheimani
 
800 W. Campbell Road
Richardson, TX 75081-2426
United States

 (972) 883-4158
 Nonprofit College or University
Abstract

Nanotechnology has yet to live up to its promise of exploiting properties which emerge at the nanoscale because of the lack of manufacturing precision to control the nanoscale dimensions, thus denying society many energy saving materials and applications. This project targets a key component of an Atomically Precise Manufacturing system: a high-speed sub-nm-precision manufacturing platform for atomic precision patterning and hierarchical assembly using arrays of MEMS actuators. The overall objective of this project is to devise a platform for Scanning Tunneling Microscope (STM)-based high-speed and high-throughput imaging and lithography. This will be done by designing the requisite hardware, software and control algorithms which comprise such a system. Our approach uses novel control systems and later, local digital control to enable large arrays. We will: (1) Design and build a high-speed 2Degrees Of Freedom atomic-precision nanopositioner for STM-based imaging and lithography. This nanopositioner will enable accurate positioning of the STM heads over the atomic lattice with an accuracy of ±1Å. It will be equipped with feedback control loops to guarantee stability, robustness and repeatability of operation; (2) Design and build an array of on-chip Si On Insulator-MEMS STMs. Each device will have full STM functionality and will comprise a high-bandwidth 1 Degree Of Freedom MEMS nanopositioner that moves in the vertical direction to servo the gap between the tip and sample. These MEMS devices can be stacked in close proximity to one another so that they may be used collectively to image a large area or write a single large pattern; and (3) Design a feedback control system that ensures high-bandwidth parallel operation of the STM heads, and increases the tip lifetime during imaging and lithography.

* Information listed above is at the time of submission. *

US Flag An Official Website of the United States Government