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Photonic Memory Controller Module

Award Information
Agency: Department of Energy
Branch: N/A
Contract: DE-SC0017172
Agency Tracking Number: 235577
Amount: $1,499,926.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: 04a
Solicitation Number: DE-FOA-0001794
Timeline
Solicitation Year: 2018
Award Year: 2018
Award Start Date (Proposal Award Date): 2018-05-21
Award End Date (Contract End Date): 2020-05-20
Small Business Information
41 Aero Camino
Goleta, CA 93117-3119
United States
DUNS: 191741292
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Leif Johannson
 (805) 967-4900
 info@freedomphotonics.com
Business Contact
 Milan Mashanovitch
Phone: (805) 967-4900
Email: info@freedomphotonics.com
Research Institution
N/A
Abstract

As computational density for high performance computing and big-data services continues to scale, performance scalability of next generation computing systems is becoming increasingly constrained by limitations in memory access, power dissipation and chip packaging. The processor-memory communication bottleneck, a major challenge in current multicore processors due to limited pin-out and power budget, presents a detrimental scaling barrier to data-intensive computing. General statement of how this problem is being addressed: A consortium team of small businesses and leading researchers that includes experts from photonics processor-memory architecture, III/V photonic laser design/fabrication, silicon photonics design/fabrication, photonics packaging and assembly, and FPGA-based high performance memory controller IP development to collaboratively develop a commercialization path for a Photonic Memory Controller Module (P-MCM). What was done in Phase I: Columbia University coordinated the working group and subgroups to provide the system architecture and specifications for each small business consortium team members. Columbia developed high performance memory controller IPs and interfaces in FPGAs platform. Freedom Photonics developed the programmable, tunable laser using mature InP/GaAs processing. Analog Photonics developed the photonic transceiver and interconnect fabrics using silicon photonic processing. PLC Connections packaged the photonic transceiver and interconnect fabric chips and tunable laser chips and provide a low-loss and robust optical coupling mechanism. What is planned for the Phase II project: Columbia University will continue to coordinate the working group and subgroups to provide the system architecture and specifications for each small business consortium team members. Columbia will update high performance memory controller IPs and interfaces in FPGAs platform to meet Phase II goals and perform a final end of Phase II P-MCM demonstration. Freedom Photonics will develop and package a 17-channel integrated source laser array. Analog Photonics will design, fabricate and package switch, photonic transceiver, driver IC and interconnect fabrics using silicon photonic processing. PLC Connections will develop high density, low cost I/O packaging technology to interconnect the ICs and components developed in this program using dense fiber arrays to provide a low-loss and robust optical coupling mechanism, and deliver packaged prototypes to Columbia for system integration and demonstration. Commercial Applications and Other Benefits: The Photonic Memory Controller developed have wide commercial applications in data center and telecom markets.

* Information listed above is at the time of submission. *

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