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Non Destructive Trusted FPGA Verification

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA9453-18-C-0267
Agency Tracking Number: F171-068-0676
Amount: $749,999.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: AF171-068
Solicitation Number: 2017.1
Solicitation Year: 2017
Award Year: 2018
Award Start Date (Proposal Award Date): 2018-09-20
Award End Date (Contract End Date): 2020-09-20
Small Business Information
531 Esty Street
Ithaca, NY 14850
United States
DUNS: 603978321
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Jason Dickens
 (607) 273-7340
Business Contact
 Derek Burrows
Phone: (607) 273-7340
Research Institution

Field Programmable Gate Arrays (FPGAs) can provide electronic system designs with a high degree of relatively inexpensive customization. Unfortunately, the fabrication facilities are located in untrusted facilities. This prevents their use in applications requiring a high degree of safety or security. Hidden functionality could potentially be inserted during manufacture. These Trojans can be used for many malicious purposes including: denial of service, data exfiltration, bypassing security, and reducing reliability of critical systems.GrammaTechs solution takes advantage of FPGA architecture and its re-programmability to produce robust tests which do not rely on sensitive supply current analysis. The approach includes new techniques which will address the limitation in current hardware Trojan detection methods.During Phase I, GrammaTech developed a prototype hybrid Trojan detection system and demonstrated detection algorithms that improve upon the ability to detect even the most subtle of Trojans. The Phase II, effort will augment the results of the Phase I with the testing of a larger population of devices and the testing of Trojan-infected devices. Additional data analysis techniques will be applied to further enhance the detection sensitivity. The result will be a Trojan detection system that can be adapted to verify trust in different FPGA devices.

* Information listed above is at the time of submission. *

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