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Novel Integration Technologies for Infrared Focal Plane Array Application


TECHNOLOGY AREA(S): Electronics 

OBJECTIVE: Evaluate, develop and demonstrate the novel application of emerging commercial technologies for heterogeneous integration of infrared photodetector arrays and CMOS-based multiplexing circuitry. 

DESCRIPTION: The Army needs the highest performance infrared sensors for tactical and strategic overmatch. Mission-specific applications for high-sensitivity sensors extend across multiple infrared bands, including long wavelength (8-12 microns). These requirements have led to the development of infrared focal plane arrays (IRFPA) with large formats (~ megapixel) and small pixel pitch (~ 10 micron). Such IRFPAs consist of an array of photodetectors hybridized to a CMOS-based multiplexing circuit (ROIC), which reads out the photo-generated current to create useful imagery and information. ROIC design has evolved to improve sensor performance and to include more on-chip functionality, such as digitization and signal processing. Most current IRFPAs are fabricated using flip chip (C4), die-to-die bonding/interconnect processing. Technological developments in commercial, three-dimensional (3D), wafer-to-wafer level integration are leading to interconnect densities [1, 2, 3] relevant to state-of-the-art IRFPA applications. Such 3D integration offers potential, significant cost savings for IRFPA fabrication, particularly, if wafer-to-wafer integration can be realized. However, many technical challenges and uncertainties exist to such an implementation, including, but not limited to: limited thermal tolerance of typical infrared devices; wafer size mismatch between detector and ROIC; potential contamination/diffusion issues associated with interconnect materials (Cu, W, Sn etc.); compatibility with cryogenic operation, to include thermal cycling reliability. Non-technical challenges need also be considered such as: actual cost benefits, given the potential technical constraints, relatively small production quantities [4]; security, trustworthiness of hardware, foundry etc. [5]. The goals of this project are: to evaluate and analyze 3D integration technologies in the context of IRFPA hybrid assembly; to develop/modify a 3D integration process compatible with a relevant IRFPA product; to implement, demonstrate, test and evaluate, in hardware, application of 3D integration to a relevant IRFPA product. For the purposes of this project, an IRFPA product that is relevant to Army requirements is defined by the following characteristics: cryogenically operated; cut-off wavelength > 5 microns; format > 640 x 480 pixels; pixel pitch < 15 microns. 

PHASE I: The performer shall evaluate and analyze 3D integration technology in the context of IRFPA fabrication: i.e. detector array to ROIC hybridization. This analysis shall include technical, cost and security considerations. This analysis shall consist of a trade study of various processes and parameters constrained by compatibility with IRFPA processing and operation: for example, comparison of wafer-to-wafer, die-to-wafer and die-to-die integration modes. Based upon the results of this analysis, the performer shall develop a plan to develop, to implement and to demonstrate 3D integration technology in an IRFPA product that is relevant to Army requirements. 

PHASE II: The performer shall design and develop a 3D integration process that is compatible with a relevant IRFPA product based upon analysis and planning of Phase I. The performer shall implement, demonstrate, test and evaluate the resulting process, in hardware, in a relevant IRFPA product. 

PHASE III: The performer shall transition technology to appropriate foundries and/or industries for commercial implementation of resulting processes, products and/or intellectual property. Dual use applications include: machine vision, autonomous vehicles, security, process control, environmental monitoring, scientific instruments, and astronomy. 


1: Wang, L, et al., "Direct Bond Interconnect (DBI®) For Fine-Pitch Bonding in 3D and 2.5D Integrated Circuits," 2017 Pan Pacific Microelectronics Symposium, 6-9 Feb. 2017.

2:  Gao, G. et al., "Scaling Package Interconnects Below 20μm Pitch with Hybrid Bonding," 2018 IEEE 68th Electronic Components and Technology Conference, pp. 314-322 [DOI: 10.1109/ECTC.2018.00055]

3:  Fournel, F., et al., "From Direct Bonding Mechanism to 3D Applications," 2018 IEEE International Interconnect Technology Conference (IITC), pp. 175-178, 4-7 Jun. 2018. [DOI: 10.1109/IITC.2018.8430293]

4:  Lujan, A., "Comparison of Package-on-Package Technologies Utilizing Flip Chip and Fan-Out Wafer Level Packaging," 2018 IEEE 68th Electronic Components and Technology Conference, pp. 2089-2094, [DOI 10.1109/ECTC.2018.00313]

5:  Knechtel, J., et al., "Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration," IPSJ Transactions on System LSI Design Methodology, vol. 10, pp. 45-62, Aug. 2017 [DOI: 10.2197/ipsjtsldm.10.45]

KEYWORDS: Infrared Focal Plane Array, IRFPA, 3D Integration, Heterogeneous Integration, Wafer Bonding, Direct Bonding, Interconnect, Hybridization, Flip Chip Bonding 

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