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Backside Inspection Frontside Electrical Stimulation System

Description:

TECHNOLOGY AREA(S): Sensors, Electronics, Battlespace 

OBJECTIVE: Develop a semiconductor device Fault Isolation tool that works across a wide range of technology processes. 

DESCRIPTION: Infrared (IR) Microscopes are used in the Failure Analysis (FA) and Fault Isolation (FI) of silicon-based semiconductor devices because of the fact that silicon is transparent to near-IR (NIR) light. Some of these microscopes use Charge-Coupled Device (CCD) cameras that are specifically designed for the NIR wavelengths, and others use a NIR wavelength laser with a scanner. These tools are used to find specific areas of interest, and are particularly effective when using them to find faults on Flip Chip, or Controlled Collapse Chip Connection (C4) devices where the bond pads are connected directly to the package substrate, leaving the bulk silicon (backside) fully exposed. A common alternative to Flip Chip is wire-bonded devices where the bulk silicon of the device is mounted to the package and bond wires attach the bond pads to a lead frame on the package. Most of the State-of-the-Art (SOTA) FI tools have been developed specifically for Flip Chip devices. This presents a challenge when attempting to use these SOTA FI tools with legacy wire-bonded devices, or even unpackaged C4-based devices (full/partial wafers, bare die, etc.). One of the requirements for these SOTA FI tools is that the device must be electrically stimulated in order to detect the faults (open circuits, short circuits, etc.) When inspecting a wire-bonded device using these tools, one must inspect the frontside, as that is the only side that is accessible. This limits the FI capabilities to detecting faults that occur on the topmost metal layer, and any faults present in the circuitry below is blocked by the preceding layers above. If instead, the device could be stimulated (e.g. micromanipulator probing, probe card, etc.) from the frontside while still allowing the FI tool to access the backside of the device, the FI capabilities would be improved greatly, allowing the tools to be used with both packaged and unpackaged parts. Most of the SOTA FI tools include a Solid Immersion Lens (SIL) that makes physical contact with the device under test (DUT), providing high magnification (350X) with a very high Numerical Aperture (NA) (>2.5). One of the main challenges is handling the devices. When inspecting a device with the SOTA FI tools, typically they are backside-thinned such that the remaining silicon thickness (RST) is 100µm or less, depending on the tool. With most of the bulk silicon removed, there is little structural support remaining; this results in a very fragile device. When using a SIL on a Flip Chip device, the package substrate provides the structural support needed to prevent damaging the thinned DUT. The innovative development of a tool that can be used to probe the frontside bond-pads of a device while allowing for simultaneous backside inspection is desired. DIRECT TO PHASE II: DMEA will only accept Direct to Phase II proposals. 

PHASE I: Perform a study on different methods for electrically stimulating various semiconductor microelectronic devices while allowing for access to the backside for inspection. The end result of Phase I is a feasibility study report, which demonstrates all the rational justifications for studying the proposed technique. The report will explicitly addresses the following items: 1. The developed tool shall be compatible across a wide range of semiconductor microelectronics devices, including but not limited to wire-bonded, Flip Chip, full wafers, bare die, etc. 2. The developed tool shall be capable of electrically stimulating the DUT from the frontside while simultaneously being able to inspect the backside of the device with a backside inspection tool without blocking photoemission transmission. 3. The developed tool shall be capable of precisely and accurately positioning each probe from the top side. The feasibility study shall identify the characteristics of the probing system, including but not limited to probe tip sizes, accuracy, precision, maximum number of probes (micromanipulators and probe card), etc. 4. The developed tool shall be capable of allowing the use of a SIL on the backside of the DUT while being electrically stimulated. 5. The developed tool shall be capable of moving all of the probes together independently from the DUT, such the probing orientation can be used across multiple devices without moving each probe one by one while maintaining the same Field of View on the backside inspection tool. The feasibility study shall identify the travel range limitations of the stage. 6. The developed tool shall be capable of docking to DMEA’s backside inspection FI tool interface without exceeding 100lbs. 7. The developed tool shall be capable of interfacing with Industry standard Integrated Circuit (IC) electrical testing equipment. 8. The feasibility study shall identify the DUT size limitations, including but not limited to both the upper and lower limits for sample size, thickness, etc. 9. The feasibility study shall identify the DUT feature size limitations, including but not limited to the smallest bond-pad size that can be electrically stimulated by the system, bond pad pitch, bond pad spacing, etc. 10. The feasibility study shall identify the minimum force required to be applied by the electrical stimulation system in order to maintain electrical connectivity without damaging a thinned device for various thicknesses less than or equal to 100µm, including but not limited to 100µm, 50µm, 25µm, 10µm. 11. The feasibility study shall identify the DUT mounting methodology and any associated transmission loss percentage induced by the DUT mounting methodology. Deliver a report of research and innovation, including a notional list of possible components, a list of all the facility requirements and a program plan for system development. If any of the above restraints cannot be adhered to, the report must include relevant research and rationale. If adhering to the above restraints is possible, but not financially feasible, the report must include relevant research and rationale. FEASIBILITY DOCUMENTATION: Offerors interested in participating in Direct to Phase II must include in their response to this topic Phase I feasibility documentation that substantiates the scientific and technical merit and Phase I feasibility described in Phase I above has been met (i.e. the small business must have performed Phase I-type research and development related to the topic, but from non-SBIR funding sources) and describes the potential commercialization applications. The documentation provided must validate that the proposer has completed development of technology as stated in Phase I above. Documentation should include all relevant information including, but not limited to: technical reports, test data, prototype designs/models, and performance goals/results. Work submitted within the feasibility documentation must have been substantially performed by the offeror and/or the principal investigator (PI). 

PHASE II: Based on the aforementioned study and applicable innovation, produce a fully functioning prototype that adheres to all the constraints listed above. Test the prototype and deliver along with at least four (4) samples. Two (2) of the sample should represent the smallest and thinnest sample size the system is capable of supporting and should show the process repeatability between both samples. The other two (2) samples shall represent other sample cases, demonstrating the wide range of devices supported and the flexibility/universality of the system. Deliver a complete Bill of Materials (BOM), including all components used, manufacturers, part numbers, quantities, technical datasheets, facility requirements, and CAD drawings for each component and a complete CAD assembly for the completed prototype. 

PHASE III: There may be opportunities for further development of this system for use in a specific military or commercial application. During a Phase III program, offerors may refine the performance of the design and produce pre-production quantities for evaluation by the Government. The Backside Inspection Frontside Electrical Stimulation System would be applicable to both commercial and government semiconductor device research and FA. Government applications include FA and FI of semiconductors. Commercial applications include FA and FI of semiconductors. 

REFERENCES: 

1: Dan Bockelman, et al. Multi-Point Probing on 65nm Silicon Technology using Static IREM-based Methodology. ISTFA 2005.

2:  John H. Lau. Status and Outlooks of Flip Chip Technology. ASM Pacific Technology. 02/20/2017

3:  Kenneth Krieg, et al. Electrical Probing and Surface Imaging of Deep Sub-Micron Integrated Circuits. ISTFA 1999.

4:  M.S. Wei, et al. Sample Preparation for High Numerical Aperture Solid Immersion Lens Laser Imaging. ISFTA 2014.

KEYWORDS: Fault Isolation, Failure Analysis, Electrical Stimulation, Probing 

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