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Near Atomic Spatial Resolution Electrical Characterization


TECHNOLOGY AREA(S): Materials, Sensors, Electronics, Battlespace 

OBJECTIVE: Develop a technology similar to a scanning probe microscope capable of simultaneously measuring the variation of surface potential/Local Density of States and topography to image and identify defects with near atomic spatial resolution in modern electronic devices. 

DESCRIPTION: The demand for higher computing speeds for electronic systems has resulted in the shrinkage of devices features and a higher density of transistors in integrated circuits (ICs). This shrinkage of device geometries has induced a variety of challenges for the metrology of electronic devices including the measurement of narrow trenches and holes for failure analysis and in-line process control. There are multiple techniques for characterization of electronic devices such as critical dimension scanning electron microscopy (CDSEM), transmission electron microscopy (TEM), optical scatterometry (OCD), atomic force microscopy (AFM) and x-ray microscopy (XRM). However, there are limitations associated with each of these techniques with respect to preservation of device functionality, low spatial resolution, and/or small field of view. For instance, both CDSEM and TEM induce charging of non-conducting samples, and they provide information only about specific sections of samples and require destructive sample preparation. AFM techniques requires less sample preparation; however, it often offers a maximum scanning area of 150 by 150 micrometer square in comparison to SEM with millimeter square scan sizes. The sample preparation for XRM technique is also less destructive; however, this method provides a maximum spatial resolution of 30 to 40 nm and in most cases is very expensive as it requires light synchrotrons for generation of x-rays. Alternatively, kelvin probe force microscopy (KPFM), which is an AFM based apparatus provides nanometer-scale imaging of the sample surface potential to characterize the electronic properties of semiconductor devices to determine various characteristics of samples ranging from doping and composition to defects in dielectrics. However, KPFM does not offer near-atomic scale imaging, which can be used to acquire information on processes that induced defects and their impact on the functionality of electrical devices. Hence, the performer is expected to evaluate, develop and/or integrate techniques to simultaneously measure surface potential and image surface topography with high spatial resolution (less than 10 Å) to identify defects in transistors. 

PHASE I: Perform a feasibility study on various methods to measure surface potential while imaging to identify defects for characterization of electrical devices. The end result of this performance is a report that provides all the rational justification for the proposed technique. The feasibility report should address the following constraints: ‒ The proposed method shall provide near atomic (less than 10 Å) topographic imaging and measurement of surface potential. ‒ The proposed method shall require non-destructive sample preparation to preserve device performance. ‒ The proposed method shall not alter device functionality. ‒ The proposed method shall consider the varying materials present in semiconductors (including but not limited to silicon, silicon dioxide, silicon nitride, copper, aluminum, sapphire, tungsten, tantalum, etc.). ‒ The proposed method shall be capable of defect characterization in semiconductor transistors including but not limited to gate oxides of Fin Field-effect transistors (FinFETs).  

PHASE II: Phase II will result in building, testing and delivering a fully functional prototype or technology of the method developed in phase I. Deliver the testing data and the samples for which the experiments were performed. Deliver all the supporting documents, including CAD drawings, analysis, developed hardware and software components, and process flows. At minimum four samples need to be delivered. Two samples will represent transistors with the smallest technology node that the prototype can characterize. The other two samples will represent other materials systems to support the constraints noted in Phase I. The performer is expected to show repeatability between similar samples having the same materials and features. 

PHASE III: Phase III will result in the expansion of the prototype system in Phase II into a tested pre-production system. The system encompasses a technique capable of simultaneous surface potential measurement and topographic imaging for precise defect identification. This system has applications for evaluating failures of integrated circuits (ICs) both in commercial and government sectors. 


1: M. K. Lee, et al., Applications of AFM in Semiconductor R&D and Manufacturing at 45 nm Technology Node and Beyond, Proc. of SPIE 7272 (2009) 72722R-1 to 72722R-12.

2:  W. Melitz, et al., Kelvin probe Force Microscopy and its Application, Surface Science Reports 66 (2011) 1–27.

3:  F.M. Battiston, et al., Combined Scanning Tunneling and Forcemicroscope with Fuzzy Controlled Feedback, Appl. Phys. A 66 (1998) S49–S53.

4:  J. Deng, et al., Nanoscale X-ray Imaging of Circuit Features without Wafer Etching, Phys Rev B. 95 (2017).

KEYWORDS: SPM, Surface Potential, Characterization, Failure Analysis, Semiconductor Devices, ICs 

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