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Continuous-Time Digital Signal Processing (DSP) Using Reconfigurable Devices


TECHNOLOGY AREA(S): Info Systems, 

OBJECTIVE: Modern missile systems require tremendous amounts of signal and information processing using constrained resources in an extreme environment. Multi-spectral sensors, high-bandwidth communications, and supersonic flight control demand significant processing power, while space and weight constraints limit available power and heat dissipation. It is uncertain that conventional Digital Signal Processing (DSP) approaches can provide the increased performance required in next generation missile systems. To meet this need, alternatives to conventional, power-hungry digital processing approaches are desired. A promising novel approach is continuous-time digital signal processing (CTDSP), which achieves similar or improved performance while offering a significant decrease in power and heat dissipation requirements [1]. In particular, continuous-time algorithms that can be implemented on reconfigurable hardware including field programmable gate arrays (FPGAs) can enable the flexible design of future missile systems. Because the power reduction of this technique is application-specific, an exact benefit to Army systems cannot be quantified at this time; however, power savings of as much as a factor of 3 have been reported [2]. This effort is designed to impact the Long Range Precision Fires and Air and Missile Defense Army Modernization Priorities. 

DESCRIPTION: Continuous-time digital signal processing (CTDSP) offers a promising alternative to conventional digital signal processing (DSP) for systems constrained by size, weight, power and cost [3]. The defining attribute is the use of continuous digital states instead of discretely clocked samples. Gate outputs switch as input signals change, in contrast to conventional DSP where gate outputs update with a fixed frequency clock. As such, CTDSP can be described as unclocked digital processing. The primary potential benefit of CTDSP is a reduction in power consumption and heat generation due to reduced switching for low-activity signals. As CTDSP matures, the standard modules and functions that underlie many of the most common signal processing algorithms must be redesigned to operate using unclocked logic. Operations including linear filters, mixers, correlators, and even simple mathematical functions require a new design approach. Many key algorithms have been successfully demonstrated, primarily filters using FPGAs [3] and application specific integrated circuits (ASICs) [4]. Importantly, the development of conventional digital systems has been greatly aided by the widespread use of reconfigurable devices such as FPGAs. The inclusion of reconfigurable devices not only accelerates initial development but also facilitates maintenance and upgrade of fielded systems. To exploit recent advances, the development of continuous-time digital signal processing algorithms beyond linear filter networks that work on reconfigurable digital devices is highly desirable. These algorithms may use amplitude quantization of analog input signals but enable continuous, unclocked processing of the digital signals. Targeted algorithms will enable the common signal processing operations required for communications, sensing, and control that are typical of modern missile systems. Challenges include continuous-time digitizing of analog signal input, algorithm design, resource optimization, amplitude quantization effects, bandwidth limitations, and error correction or tolerance. Preferred designs will be vendor agnostic and portable across reconfigurable devices, with minimal tuning that is device dependent. The intent of this solicitation is to develop a suite of CTDSP algorithms to enable low-cost, low-power, reconfigurable signal-processing devices to support a large variety of applications. As such, the solicitation is not limited to a particular application or performance specification. 

PHASE I: Conduct a design study to identify important signal processing blocks for implementation using continuous-time digital circuits on a reconfigurable device. These important processing blocks should, at a minimum, implement lowpass, highpass, bandpass, and notch filters as well as modulation. Simulation and theoretical analysis will identify a preferred concept design for signal representation and modularization of operations. Consideration will be given to analog signal interface, resource requirements, quantization effects, and portability within reconfigurable architectures. 

PHASE II: Finalize an optimized suite of continuous-time signal processing tools implementable on reconfigurable gate arrays to support various signal processing requirements typical in a missile system. Performance metrics will establish improved performance compared to conventional DSP approaches in terms of size, power, heat dissipation, cost, and reconfigurability. Potential military and commercial applications will be identified and targeted for Phase III exploitation and commercialization. 

PHASE III: The development of continuous-time digital signal processing to meet signal processing requirements using reconfigurable gate arrays enables a significant leap-ahead technology for signal processing to support communications, remote sensing, and control. These technologies offer potential benefits across a wide swath of communications and sensor networks for both military and civilian applications. 


1: Y. Tsividis, "Continuous-time digital signal processing," Electronics Letters 39(21), 1551 (2003).

KEYWORDS: Digital Signal Processing (DSP), Continuous-Time Digital Signal Processing (CTDSP), Field Programmable Gate Arrays (FPGAs) 

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