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Reconfigurable Computer Architecture for Flexible Input / Output (I/O)


TECHNOLOGY AREA(S): Electronics, 

OBJECTIVE: Develop a reconfigurable computing-based platform that provides reprogrammable hardware implementations for multiple communication protocols, cryptographic algorithms, and heterogeneous architectures for ground vehicle sensor/system integration (e.g. signal concentration for routing through Next Generation Combat Vehicle slip ring), hardware accelerated capability insertion, and mitigation of semiconductor device obsolescence. 

DESCRIPTION: The Army has long been interested in leveraging the benefits of Field Programmable Gate Array (FPGA) and System on Chip (SoC) technologies to mitigate performance and obsolescence issues associated with the extended life cycle of Army weapon systems. Historically the Army spends over a decade to design, test, and field a new weapon system and this means that, in many cases, the computing hardware and communication technology is obsolete by the time it is fielded [1]. To decrease this impact of this, weapon system functionality can often be migrated to software but this can be detrimental when the software implementation incurs a significant performance penalty or when the software cannot be written portably, resulting in code that is tightly coupled to a specific microprocessor or microcontroller; this is especially true when the software performs safety-critical functions, needs to perform deterministically and targets a specific instruction set architecture (ISA). Incorporation of FPGA technology has traditionally been recognized as one way to protect against electronics obsolescence while preserving the ability to implement performance upgrades [2]. High-level synthesis languages and semiconductor intellectual property (IP) cores have matured to the degree that it may be possible for the Army to leverage them on a computing platform which can incorporate open-source soft-core processors (e.g. RISC-V) to mitigate software obsolescence [3], readily instantiate new circuitry via logic synthesis to support emerging capabilities (e.g. artificial neural networks), and also provide a path for updating to different communication technologies primarily through logic synthesis (e.g. migration of 1 Gigabit Ethernet to 10 Gigabit Ethernet). This topic seeks innovative approaches to leverage reconfigurable computing and FPGA technology to increase the flexibility, longevity, capabilities, and performance of computing platforms within Army ground vehicles, specifically used to implement emerging capabilities on a Bradley and/or Optionally-Manned Fighting Vehicle (OMFV), to process multiple types of I/O and is reconfigurable to evolve along with vehicle programs and technology. A highly competitive solution should, with minimal changes to the electronics, provide reconfigurable: (1) hardware acceleration for running selectable cryptographic algorithms (e.g. Secure Hash Algorithm [SHA]-256, SHA-512, Advanced Encryption Standard [AES]-128, AES-256) (2) hardware-supported video processing and distribution (3) heterogeneous architecture to support simultaneous hosting of real-time, safety-critical and general purpose Linux software (4) support for multiple channels of serial communication (e.g. RS-422, RS-232, Controller Area Network [CAN], Inter Integrated Circuit [I2C]) (5) support for multiple channels of Ethernet (e.g. Gigabit Ethernet [GbE], 10 GbE, Audio-Video Bridging [AVB]/ Time Sensitive Networking [TSN]) (6) support for multiple types of analog and discrete signals (e.g. audio, RS-170) (7) Provides an Interface Configuration Document (ICD), hardware performance specification, and Technology Readiness Level (TRL) 6 test report. 

PHASE I: Investigate the design space for reconfigurable computing based, ruggedized platforms. Define metrics for assessing obsolescence risk reduction and re-configurability, as well as difficulty/cost associated with using reconfigurable computing technology, IP cores, hardware, and tools. Develop initial reference designs to illustrate I/O processing/conversions, communications/cryptographic migration, and heterogeneous computing scenarios. 

PHASE II: Fully develop the technology and demonstrate general features of the Flexible I/O platform, which consists of hardware, firmware, software, and synthesizable logic in the form of hardware description language (HDL) or IP cores. Evaluate using the metrics defines in Phase I. Execute selected computing/migration scenarios and collect metrics as defined in Phase I. Perform additional testing to assess performance and operational impacts and provide an ICD and hardware performance specification. 

PHASE III: Phase III applications include deploying Flexible I/O platform in the Bradley or OMFV vehicle for processing/distribution of 3rd Gen FLIR video information and signal compression/decompression for transmission through slip-ring. Phase III potential applications include the use of Flexible I/O for long-life span, advanced Internet-of-Things (IoT), Industrial Control System (ICS), medical imaging devices, or autonomous systems. 


1: Research and Technology Organization, "Strategies to Mitigate Obsolescence in Defense Systems Using Commercial Components", DTIC June 2001

KEYWORDS: FPGA, Softcore Processor, Heterogeneous Computing, Reconfigurable Computing, IP Cores, Obsolescence 

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