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SiC BiCMOS Platform Development


RT&L FOCUS AREA(S): Microelectronics


OBJECTIVE: To develop a BiCMOS platform utilizing SiC wafer to achieve high temperature operation and high voltage/power integration.

DESCRIPTION: As a result of almost four decades long investment on SiC technology by DoD and technical breakthroughs achieved by private sectors, affordable high-voltage SiC MOSFETs debut in the market recently [1][2]. The 650+V SiC MOSFETs become popular switching devices in data center, renewable energy, and even electric vehicle applications thanks to excellent energy efficiency and reduction in the power conversion system size and weight.

While discrete SiC power devices are successfully commercialized, separate efforts to develop SiC integrated circuits (ICs), that can be used in high temperature and high radiation environments, have continued for a decade. Those ICs were mostly based on non-CMOS, (i.e. bipolar transistor [3], MESFET [4] and JFET [5][6]) due to many technical barriers in SiC CMOS technology such as low channel mobility, uneven performance of NMOS vs. PMOS, forming resistive ohmic contacts, and gate oxide reliability.

More recently, advantages such as convenient digital circuit design using standard libraries and low power consumption of CMOS configuration drive big corporations [7][8] and small businesses [9][10] to jump into the SiC CMOS IC development competition. Despite these aspirations and effort, decent SiC CMOS technology development will not be easy to overcome the fundamental material properties of SiC including high gate oxide/SiC interface states.  

The goal of this solicitation is to develop and demonstrate a SiC BiCMOS platform that can be applied up to 300°C ambient temperature. Base materials for this solicitation include, but are not limited to bulk or epitaxial SiC wafer, Si/SiC direct bonding (Si/SiC DB) wafer, or Si-epitaxial grown on SiC substrate (Si-epi/SiC) wafer.

PHASE I: Perform a Feasibility Study that addresses the gate oxide related parameters such as channel mobility, gate tunneling current, time-dependent dielectric breakdown (TDDB), bias temperature instability (BTI), and yield (extrinsic failure rate). Key parameters related to the gate oxide should meet requirements as below.  

- NMOSFET channel mobility > 50 cm2/V·s

- PMOSFET channel mobility > 10 cm2/V·s

- Threshold voltage shift (for NMOSFET and PMOSFET) < ±500 mV at bias-temperature stress during mean time to failure

When Si/SiC DB or Si-epi/SiC wafers are used, Si/SiC interface and across-wafer uniformity should be characterized by various imaging tools and spectroscopy. All junction combinations between (n and p-type) Si and (n and p-type) SiC have to be characterized electrically to monitor the ohmic and p-n junction behavior. Key parameters related to SiC/Si interface should meet requirements as below.

- Void free and continuous SiC/Si interface throughout entire wafer

- Bonding interface thickness (thickness of SiO2, amorphous Si or carbon rich region) < 10 nm

- Bonding interface state density < 1x1012  eV-1cm-2

If those key parameters are not met the requirements, detailed plans for improvement of those reliability and performance parameters during phase II must be proposed.

PHASE II: Prototype deliveries of phase II are development of wafer fabrication process and Process Design Kit (PDK). Based on the process, statistical data of critical parameters and reliability (mostly gate oxide related) data for technology qualification are to be reported. For CMOS transistors and high-voltage LDMOS, BSIM (or BSIM equivalent or modified BSIM) models incorporating statistical data shall be included in the PDK.

During the first year of phase II, TCAD simulations on n-channel and p-channel LDMOS (45V, 120V, and 650V) and other active and passive devices are necessary to define device architecture, dimension, and doping profile. Wafer processing modules (gate/field oxidation, isotropic/anisotropic etch, implant, activation/annealing, and contact/interconnect/pad metallization) on SiC or Si/SiC wafer should be developed. When SiC bulk or epitaxial wafer is used, process development should be carried out including efforts to improve gate oxide integrity, PMOS transconductance, source/drain/body ohmic contacts, and passive components temperature dependency. When Si/SiC wafer is used, wafer bonding or Si epitaxial processes, which can reproduce Si/SiC wafers, must be identified. All the process modules should be matured and stabilized. 

During the second year of phase II, all BiCMOS platform device components, which comprise of core logic CMOS transistors, analog MOSFETs (for current mirrors, differential pairs, etc), bipolar transistors, passives (diffusion and poly resistors, gate oxide or MIM capacitors), and high-voltage (45V, 120V, and 650V) LDMOSs are to be fabricated on a single die, and characterized at temperature range over -55C to 300C. Performance of those devices are to be improved/optimized though multiple test vehicles.

PHASE III DUAL USE APPLICATIONS: Continuous efforts may be needed to further stabilize the process flow which ensures product reliability to embody strong business case. Variations of the baseline flow are to be developed, for example, different technology nodes, gate oxide thickness, and LDMOS voltage ratings. The BiCMOS platforms could be utilized for smart power IC production, second source manufacturing or licensing.

SiC wafer platform is advantageous for high-temperature and radiation hardened ICs (when semi-insulating SiC substrates are used). On the other hand, Si/SiC wafer platform allows hybrid integration of high density Si CMOS logic and SiC high-voltage power devices. The platform could take advantage of Si/SiC heterojunction properties to enhancing LDMOS performance [11][12].

Those platforms are highly attractive to NASA’s space programs, Air Force’s aircrafts, Army’s combat electric vehicles and nuclear facilities where harsh environment electronics are required. Analog Devices’ AD8229 and ADXL206 are notable commercialized Si based products available in the market targeting oil/gas drilling, aerospace, and geothermal applications under 200°C ambient temperature. Many defense and civilian industries are anticipating SiC IC products that can operate above the Si temperature limit.

The Si/SiC DB wafer has not been commercialized simply due to lack of demand. If the Si/SiC platform development is successful, it would create demand for Si/SiC DB wafers as a base material for the BiCMOS IC production. Therefore, Si/SiC wafer manufacturing business will be a promising derivative from the platform development.

Potential Value to DoD: Because weapon systems operate under unexpected theatrical conditions, the systems have to be small, light, and energy efficient to meet size/weight/power (SWaP) goal of DoD. SiC BiCMOS ICs help to achieve the goals by making electronic modules simple, highly functional, and intelligent.  


  1. “Silicon Carbide CoolSiC™ MOSFETs,”
  2. “Announcing the Wolfspeed 650V Series of SiC MOSFETs,”
  3. Shakti Singh, “Bipolar Integrated Circuits in 4H-SiC,” IEEE Transactions on Electron Devices, 2011
  4. Viorel Banu, “High Temperature-Low Temperature Coefficient Analog Voltage Reference Integrated Circuit Implemented with SiC MESFETs,” ESSCIRC, 2013
  5. Kuang Sheng, “Demonstration of the first SiC power integrated circuit,” Solid State Electronics, 2008
  6. Philip G. Neudeck, “Demonstration of 4H-SiC Digital Integrated Circuits Above 800 °C,” IEEE Electron Device Letters, 2017
  7. N. Ericson, “A 4H Silicon Carbide Gate Buffer for Integrated Power Systems,” IEEE Transactions on Power Electronics, 2014
  8. “Raytheon explores pioneering power systems for future aircraft,”
  9. “Integrated On-Chip Power for Harsh Environments,”
  10. Monolithically Integrated Rad-Hard SiC Gate Driver for 1200 V DMOSFETs,”
  11. Baoxing Duan, “Si/SiC heterojunction lateral double-diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology,” Micro & Nano Letters, 2019
  12. Qi Li, “Novel SiC/Si heterojunction LDMOS with electric field modulation effect by reversed L-shaped field plate,” Results in Physics, 2020
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