Computerized Robotic Delayering and Polishing System

The proposed research and technical objectives in this project deal with computerized automatic delayering and polishing system that would be applicable to both commercial and government semiconductor device research and development with applications including Failure Analysis (FA), Fault Isolation (FI), and Reverse Engineering (RE) of semiconductor microelectronic devices. This project could help overcome the Diminishing Manufacturing Sources and Material Shortages (DMSMS) using an automatic reverse engineering of obsolete integrated circuits. During Phase I, the research team will optimize their existing sample-preparation tool to perform front-side delayering, backside thinning, and cross-sectioning with sub-micrometer scale precision. The team will study removal rates using the system for various semiconductor materials so that an automatic process can be developed for precision sample preparation. In Phase II, the team will produce a fully functioning prototype that adheres to all the constraints mentioned in Phase I. We will test the prototype system and deliver it along with at least 2 samples for each application, for a total of at least 6 samples. Finally, we will deliver a complete Bill of Materials, including all components used, manufacturers, part numbers, quantities, technical datasheets, facility requirements, CAD drawings and a complete CAD assembly for the completed prototype.