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Tools for Memory Hierarchy Optimization on Pre-Exascale HPC Architectures
Title: PhD, VP of Research Operations
Phone: (301) 806-9607
Phone: (858) 695-9027
DTRA uses High Fidelity Computer Codes (HFCC) to investigate weapon effects and techniques for countering Weapons of Mass Destruction (WMD). End-to-end HFCC simulations in support of the DTRA Agent Defeat Warfighter Capability will require calculations including multiple phenomena that occur in vastly different time scales (µ-sec to hours). As DTRA becomes increasingly reliant on computational modeling and simulation for these security-critical tasks, efficient use of existing computational resources and planning and optimizing for current and next-generation architectures becomes paramount. Current and upcoming supercomputing platforms feature many-core processor designs with elaborate memory hierarchies. In order to get the best performance out of these machines, DTRA’s application scientists and HFCC developers will need easy-to-use performance profiling tools to discover bottlenecks in their code. To that end, EP Analytics is developing the MemInsight tool-suite that can simultaneously analyze both memory usage and thread-level parallelism to provide intuitive and actionable performance optimization insights to code developers.
* Information listed above is at the time of submission. *