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Carbon Nanotube FET Modeling and RF circuits

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA8750-20-C-0523
Agency Tracking Number: F18B-006-0008
Amount: $749,994.00
Phase: Phase II
Program: STTR
Solicitation Topic Code: AF18B-T006
Solicitation Number: 18.B
Solicitation Year: 2018
Award Year: 2019
Award Start Date (Proposal Award Date): 2019-05-22
Award End Date (Contract End Date): 2021-05-22
Small Business Information
232 Trafalgar Lane
San Clemente, CA 92672
United States
DUNS: 079437491
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Dawei Wang
 (949) 233-2093
Business Contact
 Mark Chapman
Phone: (949) 632-4960
Research Institution
 University of California, Irvine
 Natalie Tedford Natalie Tedford
5141 California Ave. Suite 200
Irvine, CA 92697
United States

 (949) 824-2683
 Nonprofit College or University

Carbon nanotubes (CNTs) have great potential for high performance RF applications. Theoretical study has shown that the electrical current in a CNT field effect transistor (CFET) is intrinsically linear. Today, linearity is the underlying limitation in increasing the data transport densities of wireless networks. The complex modulation protocols used to achieve higher data rates requires linear amplifiers. Increasing linearity in current bulk semiconductors is done by driving higher currents through large transistor channels and limiting the RF operating region to the most linear portion of the depletion curve. This wastes power and generates heat. The intrinsic linearity of CNTs promises significant improvements in spectral efficiency without sacrificing power. To optimize CFET performance for linearity and build circuits around it, a compact model of a CFET transistor has been developed. This Phase II work focuses on fabricating devices with varying layout design which can be used for further compact model parameter extraction, and in turn, using the subsequent modeling result to guide device design and enable circuit design, thus achieving improvement in both device and circuit performance. The results of this work will guide the architectures and layouts for highly linear CFET design and aid development of commercial CFET process technology.

* Information listed above is at the time of submission. *

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