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Novel Processor Architectures for Probabilistic Computing in Survivability Controllers

Description:

OBJECTIVE: Identify novel processor architectures as alternatives to the traditional Von Neumann/Harvard/modified Harvard architecture processors for probabilistic computing and develop a low-cost computing platform utilizing probabilistic processor architectures suitable for the Space, Weight and Power (SWaP) and environment constraints of the Army ground vehicle fleet. DESCRIPTION: Future military ground vehicles, especially those with active defense and survivability components, will have increased automation requiring more and more computing capacity to distill incoming sensor data and rapidly make autonomous decisions in real-time. While traditional processor architectures are very well suited for deterministically processing relatively small data sets in real-time, as the size of the data sets grows, scaling of traditional processors within the constraints of the ground platform SWaP, environment, and cost targets becomes infeasible. The goal of this project is to identify and examine alternative candidate computing solutions for probabilistic data processing and decision making that would be cost-effective and scalable to the growing processing needs of the Army’s ground vehicle fleet. PHASE I: Phase I entails a feasibility study, concept development, theoretical performance analysis, risk analysis, cost analysis and concept design of a probabilistic processor computing platform. The study shall identify candidate processor architecture solutions, describe the pros and cons of each processor architecture, and provide a recommendation for processor selection for the next Phase. The performance analysis shall describe the theoretical worst- and best-case computational throughput and latency for a range of likely scenarios. The risk and cost analysis shall present multiple options that may reduce risk or cost or provide additional capabilities or performance. The concept design shall provide a detailed technical description of how the recommended processor technology can be integrated into a test bed for performance evaluation. Expected Deliverables: 1) Analytical report (performance, risk, cost) with conclusions and recommendations 2) Design concept report for the recommended solution PHASE II: Phase II of this effort shall focus on developing a prototype test bed based on the technology described in Phase I with various risk and cost options selected in consultation with the government POC. The contractor shall develop a prototype test bed to assess the actual performance of the selected processor solution under a range of likely scenarios and computational loads as compared to the theoretical performance documented in Phase I. The causes of any discrepancies between actual and theoretical performance shall be determined and possible solutions shall be identified. Expected Deliverables: 1) Prototype hardware and software 2) Technical Data Package (includes hardware designs, drawings, schematics; software source code and documentation) 3) Test Report PHASE III DUAL USE APPLICATIONS: In the final Phase of the project, the contractor shall mature the test bed developed in Phase II, into a final product form factor (embedded processor card, board, or box) and integrate and test the solution with other devices in a vehicle platform and demonstrate a path to commercialization. A solution that has wide appeal and relevance to other fields is preferred. The proposed processor computing platform solution will have applicability to facilitate intelligent decision making for survivability, lethality, and mobility missions for ground vehicle platforms in military applications. The commercial utility of this technology applies to autonomous driving assistance capabilities in consumer and commercial vehicle fleets. REFERENCES: 1. Neuromorphic Computing https://www.intel.com/content/www/us/en/research/neuromorphic-computing.html; 2. Edge TPU https://cloud.google.com/edge-tpu; 3. Ultra-Fast Data-Mining Hardware Architecture Based on Stochastic Computing https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4425430/; 4. Jetson AGX Xavier https://www.nvidia.com/en-us/autonomous-machines/embedded-systems/jetson-agx-xavier/; 5. Intelligence Processing Unit https://www.graphcore.ai/products/ipu KEYWORDS: Novel processor, computer architecture, probabilistic computing, neuromorphic, artificial intelligence, machine learning
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