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High Throughput Photonic Processor for AI/ML programs

Description:

OBJECTIVE: The objective of this photonic processor is to address the need of a high throughput AI/ML processor that can address full sensor resolution output without the need for pre-filtering potential throughput of 480 frames per sec or 88k targets filtered and identified in 3 minutes. A one-step over a two-step inference process. All this capability could fit into a 1 or 1.5U rack system. The current processors are an adaptation of GPU and CPU performance that does not meet the Transition Partners’ performance needs of throughput, weight, power, thermal, and size. Phase II effort will use the latest photonic LED/LCD technology to accomplish photonic processor for automatic target recognition (ATR) of various sensor (i.e., E/O, MWIR, SAR, ISAR, etc.) inputs at a throughput >75k fps at full 4K imagery. A secondary goal would be to complete a study that 1) addresses ≥100k fps and throughput ≥8K imager resolution, and 2) addresses counter-adversarial issues. DESCRIPTION: This SBIR topic is a Direct to Phase II effort. Awardee(s) will be responsible for providing their own hardware and software, chargeable to the contract, but not to exceed the maximum funding limits. During the first 12 months of the SBIR Phase II effort, neither SCO, nor its partners, will provide access to any training material, government furnished information, or equipment. Digital processing technology is reaching its limitation as circuit resolution is now at single-digit nano- (10^-9 m ) resolution compared to 1995 of single-digit micron- (10^-6 m) resolution. Resolution at this level at or near the quantum level of circuitry that affects the binary processing results of 1s and 0s only. In approaching the quantum state the system must address the fact that electrons have mass and issue that Heisenberg’s uncertainty principle states that it is impossible to measure or calculate exactly, both the position and the momentum of an object. Therefore, it is impossible to know if the value is on/off or 1 or 0 or both. As an alternative, photons can serve the same function of processing and do not have mass. Without mass, the photonic processes are not bound by Heisenberg’s uncertainty principle. At the same time a photonic processor in the 1990s was built to process 2,500 images per second in the identification of image content and was referred to as Automatic Target Recognition (ATR). This processor, using current LED and camera technology could do far faster processing and identification. A processor would be used to do training of known target types, i.e., car vs trucks, commercial vessel types, fingerprint types, or famous artist painting at the unclassified level. Application can use any type of photonic processor to address training and inference processing together or separately. Such system includes but are not limited to: Correlator (4f inference), Fourier Optics (2f), photonic quantum (inference), optical based FFTs, etc. Key is that such systems should be low power, low heat transfer, and small footprint. Proposals must: • Describe in detail how the proposed solution will take sensor data and provide a repeatable topological solution via a SCO approved test and evaluation (T&E) process. • Must develop a Zemax tool, or equivalent, within the first 9-months to describe the photonic system design and performance to receive government approval. • Must use the latest photonic 4K imaging technology or proven next-generation technology. Proposals will: • Provide a detailed description of training criteria and applicable evaluation schema. It should also explain the topological criteria for assessing imagery, and any non-selected criteria with reason why it was not used in the system. • Identify and explain all featurettes of training associated with various levels of the topology. • Address the use of Photonic RGB pixels technology for gray-scale processing. • Deliver two studies: 1. To explore next generation photonic capability with greater throughput and resolution, 2. To assess counter-adversarial capability over current neural network capability. Awardees are responsible for providing their own training corpuses, and must be able to fully describe said corpuses, what criteria will be used to teach the system, and maintain continued/regular access to said training corpus in the Phase II proposals. The training corpus may be any government, commercial, academic, proprietary, or open source data set, or a combination of any or all. Loss of access to the training corpus before or during the SBIR program will result in cessation of participation of the contract. At the close of the SBIR process, awardees will deliver to the government: • A successful prototype processor with full government use rights in a U rack configuration • Associated artifacts of all documentation required to replicate the build and use of the processor for both training and inference use. Artifacts include, but are not limited to, a fully developed reference guide and detailed schema packages, specific machine learning criteria and teaching corpus description, detailed hardware/software requirements, all algorithms and unique/proprietary software needed to run the analysis, and all internal test plans and results. • Fully trained dictionary to include at least two sensor packages. • If applicable, any open source behavior or signatures analysis and analytical tools being used, and the source for each • A completed Study on: 1. Next generation throughput (fps) and imagery resolution (≥8K) capabilities, including component sources, and 2. Counter-adversary advantages/weakness of a photonic processor over current neural network GPU processor. Awardees may use any developed efforts for other governmental or commercial opportunities, including continued service support in any Phase III options. The government shall have unlimited use rights to the resulting hardware, software, algorithms, dictionaries or other deliverables from this SBIR. PHASE I: Feasibility study to be included in tech volume per proposal submission instructions. A study will address plan system design/performance and address potential photonic risks. It must also address the specifications of size, weight, and heat transfer. Secondary would be addressing cybersecurity aspects of such a system. And finally, would like to the study to define classification plan, sources of unclassified training data, and understanding/exploitation of training featurettes and those advantages over traditional neural network approaches. The Program manager would like to see, if applicable any component or system demonstrations. PHASE II: SCO will accept DP2 proposals for a cost of up to $1.5M for 24 months. Use of Phase 1 information to build a working model of the Photonic processor for 3rd party laboratory evaluation, based on existing training data set provided by performer. SCO is looking for expertise to address 2020+ technology to address a photonic (optical) process a performance factor of 20x that of the 1990 capability of 2,500 images per second to collect imagery with a screen resolution of 2K or better. Such a system would use a combination of or existing open source neuro network operating libraries or operating systems, such as Python, Strawberry, PennyLane, Torch, TensorFlow, and others. The program manager would like delivery of working system and appropriate use and training documentation as well as a study on the cybersecurity risks for such a photonic system. PHASE III DUAL USE APPLICATIONS: Commercial applications can include but not limited to: Medical (i.e., breast or colon cancer nuclear imagery), Biometrics (i.e., non-minutia fingerprint identification and gender classification), Civil Mass Video network (i.e., highway or street Amber alert identification), next generation Self-driving vehicles, and complex drome swam multi-dimensional maneuvers. Private sector commercial potential includes uses in medical radiology imagery, autonomous vehicles, residential video security, and traffic/pedestrian city camera systems. REFERENCES: 1. Miniature Ruggedized Optical Correlator (MROC) for flight testing, SPIE Vol. 2237 Optical Pattern Recognition V, 01 March 1994; 2. MROC module for Space, SPIE Vol. 3124 • 0277-786X197, 17 Oct 1997; 3. MROC module -3rd Gene, SPIE Vol. 3386 • 0277-786X1981, 23 March 1998; 4. Use of Laser Radar Signal Processing in optical pattern recognition, Mar 1998; 5. Pattern Recognition Prototyping Tool, Nov 1997; Recognition System Rapid Application Prototyping Tool, Mar 1997; 6. Second Generation Miniature Ruggedized Optical Correlator (MROC) module, Mar 1997; 7. Performance of a second-generation miniature ruggedized optical correlator module, Oct 1997; KEYWORDS: Machine Learning, Processor Throughput, Photonic processor.
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