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Development of Integrated Infrared Focal Plane Arrays on Si, Requiring No Hybridization


TECH FOCUS AREAS: Microelectronics




OBJECTIVE: This topic seeks to develop infrared focal plane arrays (FPAs) directly onto silicon readout integrated circuitry without hybridization, operating at 2 um or longer, and using GeSn or GeSiSn absorbing layers.


DESCRIPTION:  Conventional short- and mid-wave infrared (SWIR and MWIR) detectors based on III-V (i.e., GaInSb) or II-VI (i.e., HgCdTe) materials are relatively expensive and incompatible with silicon-based readout integrated circuitry (ROIC), requiring hybridization (typically in bump bonding) which is very expensive. Technologies based on Si and SiGe are pervasive for electronic applications, but indirect energy gaps prevent their use as the active elements in optoelectronic devices. Recent progress in the material system of Group-IV alloys containing Sn (GeSiSn and GeSn) and the potential of a direct energy gap for certain compositions promises significant optical performance which is compatible with and will allow for direct integration with Si complementary metal-oxide-semiconductor (CMOS) device processing. Extremely high-quality thin films and initial proof-of-concept emitters and detectors have been demonstrated on Ge substrates but corresponding films on Si substrates suffer from high defect levels due to the lattice mismatch of high Sn content GeSiSn and GeSn alloys necessary for direct energy gap devices. The use of one or more buffer layers (e.g., a Ge virtual substrate alone or with GeSn overlayers) on Si have been used to reduce such defects but impede device integration.  Therefore, development of easily integrated emitters and detectors on Si substrates are critical for mass production of optoelectronic devices using standard CMOS production equipment and large diameter Si wafers.   A number of patterned deposition techniques have been developed for other heteroepitaxy systems (e.g. GaN on SiC or Al2O3 substrates), including nanopillars, template growth, epitaxial overgrowth, and planarization to reduce structural defects such as dislocations.  Therefore, it should be feasible to use similar approaches or develop novel ones to synthesize high quality GeSiSn or GeSn films directly on Si ROICs without the need for hybridization.  Such layers could be used to fabricate integrated FPAs operating in the SWIR or MWIR spectral regions.  Thus, if successful, this technology could be rapidly scaled and industrialized to produce low cost, large format imagers.


PHASE I: Demonstrate the feasibility of novel techniques for growth of GeSiSn and/or GeSn films directly on Si substrates. Design device structures incorporating barriers for dark current reduction, including single and complementary barrier architectures that minimize optical and electrical crosstalk between devices.  All devices should be vertical to facilitate mating to either a commercially available readout integrated circuit (ROIC) or a fanout for testing purposes. Provide experimental evidence for improved material performance of device quality epitaxial films grown on Si substrates, improved infrared absorption, and narrower X-ray rocking curves compared to typical films synthesized on traditional vacuum deposited buffer layers. Deliver a GeSiSn or GeSn film on 2" silicon wafer or larger with a minimum of 500 nm thickness for material characterization, as well as a processed variable area device die for photodetector testing.


PHASE II: Companies selected for Phase II will fabricate and characterize integrated focal plane array (FPA) detectors operating within the spectral range of 2 - 5 um on Si readout intectrated circuits (ROICs).  The external quantum efficiency (EQE) of the devices should be greater than 20% from 1.1 to more than 2.0 um and the dark current density should be less than 1 uA per sq. cm at temperatures of 200 K or greater. Deliver a silicon fanout (minimum 32 x 32, <50 um pitch) using direct deposition to verify dark current density and EQE. Deliver full FPAs for array level testing.


PHASE III DUAL USE APPLICATIONS: In Phase III, the device quality GeSiSn and/or GeSn films will be used to make infrared device structures as required by military and commercial customers including those who manufacture integrated circuits and IR optical detectors.


NOTES: The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the proposed tasks intended for accomplishment by the FN(s) in accordance with section 5.4.c.(8) of the Announcement and within the AF Component-specific instructions. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. Please direct questions to the Air Force SBIR/STTR Help Desk:



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KEYWORDS: GeSiSn; GeSn; silicon; germanium; silicon-germanium-tin; Buffer layers; Molecular Beam Epitaxy; MBE; CVD; chemical vapor deposition; epitaxial lateral overgrowth (ELO); detectors; Group IV photonics; silicon photonics; optoelectronic devices; device fabrication; growth; heterostructures; radiative recombination; quantum efficiency; semiconductor characterization; infrared; focal plane arrays (FPA)

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