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Ultra High Voltage Silicon Carbide (SiC) Gated Devices

Description:

OUSD (R&E) MODERNIZATION PRIORITY: Microelectronics

 

TECHNOLOGY AREA(S): Electronics; Materials

 

OBJECTIVE: Development of high voltage gated semiconductor device process that leverages the enhanced power handling capability of SiC, and remediates the undesirable effects (threshold voltage instability, increased interface capacitance) associated with native SiO2  growth from commercially available 4H-SiC and 6H-SiC polytypes. The process improvement and resultant performance enhancements gained will be validated by characterization of prototype devices

 

DESCRIPTION: Developmental work on wide bandgap materials has made substantial progress in recent years. The fundamental electrical properties of wide bandgap semiconducting materials are attractive to device designers due to the fact that wide bandgap devices hold the promise of substantial performance improvements over their silicon-based counterparts. In particular, Silicon Carbide (SiC) has emerged as the material-of-choice for high voltage/power applications due to its high thermal conductivity, a paramount factor for applications demanding high power dissipation. Additionally, native SiO2 growth is possible on SiC substrates, making thermal oxidation steps on SiC substrates consistent with those in traditional silicon device fabrication.  The potential to operate at higher temperatures, higher voltages, higher frequencies, and higher power densities make the utilization of SiC based devices highly desirable for future electronic systems in both commercial and defense applications.

 

A limiting factor in the development of gated high voltage devices (particularly MOSFETs), has the difficulties encountered in producing the required high quality gate dielectric. As mentioned above, SiO2 growth is applicable to SiC substrates. However, the resultant SiC/SiO2 interface contains many defects, trap states, and dangling bonds not found in the traditional Si/SiO2 interface, due to the fact that SiO2 grown on 4H, 6H, and 3C SiC polytypes has sufficient lattice mismatch to manifest in excessive interfacial defects. This has slowed the development and commercialization of gated SiC devices. The practical manifestation of interface defects in gated semiconductor devices is charge trapping. As carries tunnel from the SiC conduction band edge to the oxide interface, charge becomes trapped wherever defects are present. Trapping at these sites degrades mobility, causes threshold voltage instability, and increases the surface capacitance at the boundary. Decreased mobility reduces drive current and impacts switching speed. Threshold voltage instability reduces design functional reliability, and excessive parasitic capacitance can drastically limit switching speed. In order to fabricate reliable high voltage gated devices on SiC substrates, the defect density at the SiC/SiO2 interface must be reduced.

 

To date, formation of a high quality SiO2 dielectric remains problematic for SiC polytypes. This is particularly true for 4H-SiC and 6H-SiC, which are anisotropic in crystal structure, which results in unfavorable oxidation kinetics and less uniformity in the resultant thin films. Reduction of interface defects in gated SiC devices would result in higher performance, and enhanced reliability. In particular, this is a critical criterion for high voltage devices utilized by the DoD in mission and safety-critical applications.

 

DIRECT TO PHASE II:  DMEA will only accept Direct to Phase II proposals.

 

PHASE I: Perform a feasibility study on the selected fabrication approach to remediate the detrimental effects outlined in the preceding section of this document. The end result of Phase I is a feasibility study report, which demonstrates all the rational justifications for studying the proposed technique.  The report will explicitly address the following items:

  1. The proposed technique shall maximize the utilization of standard semiconductor tool classes (e.g. CVD, implants, etch/deposition). The feasibility study shall describe all required fabrication tools utilized to implement the proposed techniques.
  2. The feasibility study shall describe and address the shortcomings described in prior art concerning the reduction of interface defects at the SiO2/SiC interface.
  3. The feasibility study shall address the impact of SiC polytype choice on the formed dielectric.
  4. The feasibility study shall discuss the impact of growth rate on defect formation.
  5. The feasibility study shall describe the methodology and analysis techniques required to characterize the structural and composition properties of produced thin films and material interfaces.
  6. The feasibility study shall provide a detailed list of proposed follow-on tasks and technical objectives, including a proposed task schedule.
  7. The feasibility study shall describe the utilization and role of modeling and simulation in the development of the proposed technique.
  8. The feasibility study shall identify all prototype feature size limitations (e.g film thickness, gate width, minimum feature sizes).
  9. The feasibility study shall address SiC crystal orientation and its potential impact on interface defect density.
  10. The feasibility study shall address the impact of doping concentration on interface defect density.

 

Deliver a report fully describing the proposed techniques and characterization methodologies, including a notional list of fabrication tools, facility requirements and a program plan for follow-on phase development. If any of the above items cannot be fully addressed, the report must include relevant research and rationale that demonstrates their inapplicability to the proposed technique. If adhering to the above items is possible, but not financially feasible, the report must include relevant justification.

 

FEASIBILITY DOCUMENTATION: Offerors interested in participating in Direct to Phase II must include in their response to this topic Phase I feasibility documentation that substantiates the scientific and technical merit and Phase I feasibility described in Phase I above has been met (i.e. the small business must have performed Phase I-type research and development related to the topic, but from non-SBIR funding sources) and describes the potential commercialization applications. The documentation provided must validate that the proposer has completed development of technology as stated in Phase I above. Documentation should include all relevant information including, but not limited to: technical reports, test data, prototype designs/models, and performance goals/results. Work submitted within the feasibility documentation must have been substantially performed by the offeror and/or the principal investigator (PI).

 

PHASE II: Based on the aforementioned study and applicable innovation, Phase II will result in producing fully functioning prototypes of an SiC MOSFET device incorporating the proposed methodology for reducing interface defects.  The following table illustrates the minimum performance criteria for the prototype MOSFET devices. All parameters are assumed to be measured at nominal temperature (25C):

  • Table 1: Minimum MOSFET Performance Criteria (Parameter, Condition, and Value)
  • Parameter - Breakdown Voltage, Condition - VGS=0; ID=250µA, Value - 1300V
  • Parameter - Drain Current, Condition - VGS=20V, Value - 40A
  • Parameter - Threshold Voltage, Condition - ID=10mA; VDS=VGS, Value - 2.5V
  • Parameter - Drain Source Leakage Current, Condition - VDS=1200V;VGS=0V, Value - 20µA
  • Parameter - Gate Source Leakage Current, Condition - VGS=20V; VDS=0V, Value - 220nA
  • Parameter - N-Channel Mobility, Value -  >200 cm2/Vs
  • Parameter - Threshold Voltage Stability, Condition - VDD=1V;ID=100µA;VGS=-8V, Value - <3% over 100hrs

 

If the prototype does not meet the minimum requirements listed on Table 1, a rationale must be provided for each parameter specification not met, and a remediation strategy must be presented. Validated characterization results verifying that five (5) prototype devices met the specifications listed on Table 1 shall be and delivered along with at least five (5) untested samples for further testing and validation. Deliver a detailed final report that documents the manufacturing processes utilized, fabrication toolset required to perform the proposed techniques, all facilitiy requirements, and all electrical characterization and all device design data (TCAD files, modeling/Simulation results. The final report shall contain sufficient technical detail such that an entity skilled in semiconductor fabrication can repeat the presented results.

 

PHASE III DUAL USE APPLICATIONS: There may be opportunities for further development of SiC MOSFETS for use in a specific military or commercial application.  During a Phase III program, offerors may refine the performance of the design and produce pre-production quantities for evaluation by the Government.  High voltage SiC MOSFET technology has commercial and Government applications. Government applications include reduced size, ultra-high voltage power modules. Commercial applications include electric vehicle charging devices/circuitry

 

REFERENCES:

  1. Jaio, C, et al. Interface Trap Profiles in 4H-and 6H-SiC MOS Capacitors with Nitrogen-and Phosphorus-Doped Gate Oxides. Journal of Electronic Materials, 2017.
  2. Anders, M.A, et al. Are Dangling Bonds Important Interface Traps in 4H-SiC Metal Oxide Semiconductor Field Effect Transistors? Applied Physics Letters 2016.
  3. Cooper, J, et al. Fundamentals of Silicon Carbide Technology. Wiley 2014.
  4. Shur, M, et al. SiC Materials and Devices. World Scientific 2006.

 

KEYWORDS: SiC, Traps; Defects; MOSFET; High Voltage; Semiconductor

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