You are here

Side Channel Attack Testbench Emulator (SCATE)

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: W31P4Q-21-C-0004
Agency Tracking Number: D2-2533
Amount: $5,641,043.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: HR001119S0035-05
Solicitation Number: 19.105
Timeline
Solicitation Year: 2019
Award Year: 2021
Award Start Date (Proposal Award Date): 2021-04-07
Award End Date (Contract End Date): 2022-07-07
Small Business Information
100 Campus Drive
Marlborough, MA 01752-1111
United States
DUNS: 780917142
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Mark Beal
 (508) 735-1500
 mbeal@intrinsix.com
Business Contact
 Jim Gobes
Phone: (508) 658-7658
Email: jgobes@intrinsix.com
Research Institution
N/A
Abstract

Side channel analysis (SCA) and fault injection (FI) are a solid part of the relevant attack space for any chip that can be physically reached by an attacker. These hardware attacks allow key extraction from cryptographic implementations, and fault injection specifically allows complete takeover of devices. Current commercial chip design tools do not offer integrated analysis to verify resistance against these attacks at design time. The effect is that countermeasure design is a manual and error-prone process: multiple tape outs may be required, and even for experts it is nontrivial to pinpoint and mitigate sources of vulnerability. The tools we are creating allow an EDA designer without specific side channel and fault injection knowledge to create a design with countermeasures and validate them pre-tapeout. We enable secure design space exploration by allowing the designer to analyze the security and PPA impact of various countermeasures. This Phase 2 effort extends the results from the Phase 1 data that indicates the feasibility of this approach, with several challenges to still overcome. By bringing this type of analysis and countermeasure insertion into the design flow, security joins power, performance, and area in the ASIC design flow. The goal is to significantly bring down the cost of creating chips with side channel and fault attack resistance, by enabling non-expert designers to create a resistant chip without having to perform multiple tape-outs. At the maximum security setting, the chip will have 10x less leakage and 10x smaller fault probability than without this technology, and we target an iteration time of 24 hours. The result is a design process and commercializable tooling to enable a non-security-expert designer in creating a side channel and fault resistant design. The effect of this tooling is massive cost savings through reduced tape-outs, and significant increase in security.

* Information listed above is at the time of submission. *

US Flag An Official Website of the United States Government