You are here

Monolithic CMOS Integration of SiGeSn High Performance Optoelectronic Devices

Description:

OUSD (R&E) MODERNIZATION PRIORITY: Microelectronics; Network Command, Control and Communications; General Warfighting Requirements (GWR)

 

TECHNOLOGY AREA(S): Sensors; Electronics; Chem Bio Defense; Space Platforms; Materials; Information Systems

 

OBJECTIVE: Develop a SiGeSn monolithic integration technology with CMOS for optoelectronic devices operating in the wavelength range between 2.0 and 5.0 micrometers.

 

DESCRIPTION: Group-IV alloys SiGeSn (silicon germanium tin) have many unique electrical and optical properties such as a wide infrared spectrum coverage up to 12 micrometers, direct bandgap optical transition, and large feasibility of bandgap engineering by independently tuning the incorporation of Si, Ge, and Sn.  One appealing feature of the material is its low growth temperature that enables it to be monolithically integrated with CMOS circuits. Therefore the success of the material development would open possibilities for DoD to address the challenges for future infrared imaging and integrated photonics.  

Significant progress for SiGeSn material development has been made in the last a few years, which includes high quality material growth with more than 20% Sn, prototype GeSn photodetector covering the whole SWIR range, and lasers operating up to 180 K with broad wavelength coverage (2-3 micrometer).  This success is largely due to the use of low cost commercially available SnCl4 precursor and the industry standard group-IV epitaxy reactors widely adopted by IC fabs and foundries. This unique material development mode fits well with the general philosophy of Si-photonics to utilize the well-established microelectronics infrastructure to simultaneously obtain devices with high performance and low cost.

However, almost all current SiGeSn material development is based on wafer scale thin film growth.  The challenge of the large lattice mismatch between Si and GeSn is often addressed by first growing a thick buffer with multiple layers which normally have high dislocation density and could limit the final device performance.  Although all envisioned devices are expected to monolithically integrate SiGeSn with CMOS, there is very little or no research regarding how this integration should be implemented. An effective integration strategy would play a critical role for the transition of SiGeSn from material development to building useful devices.  One possible solution for the integration is to utilize a selective area growth technique: aspect ratio trapping (ART). The rationale to pursue ART growth of GeSn and SiGeSn comes with a variety of benefits, but other approaches may also be relevant. We are seeking a paradigm shift in the growth of GeSn which could solve the challenge of material development and future integration with CMOS.

 

PHASE I: Establish the integration strategy, demonstrate the feasibility of specific growth techniques or approaches of SiGeSn with sizes down to sub-micron, and clearly show a path to scale up to wafer level and integrate with CMOS.

 

PHASE II: Based on the developed technique, extensively study the material property and conduct a comparison with the thin film material in the context of device applications such as detectors and emitters; develop advanced structures for optoelectronic devices operating in the wavelength range between 2.0 and 5.0 micrometers; fabricate and characterize devices; and show significant improved device performance.

 

PHASE III DUAL USE APPLICATIONS: The technology would enable both military and commercial customers to build integrated RF photonics chips for future Radar signal processing unit and wireless communication network, as well as the large size, low cost, uncooled, low power, and digital format infrared imaging sensors used for soldiers and future Smart phones, home security cameras, and automobile night vision for enhanced driving safety.

 

REFERENCES:

  1. S. Wirths, R. Geiger, N. von den Driesch, G. Mussler, T. Stoica, S. Mantl, Z. Ikonic, M. Luysberg, S. Chiussi, J. M Hartmann, H. Sigg, J. Faist, D. Buca and D. Grutzmacher “Lasing in direct-bandgap GeSn alloy grown on Si,” Nature Photonics, vol. 9, pp. 88-92, 2015.
  2. Joe Margetis, Sattar Al-Kabi, Wei Du, Wei Dou, Yiyin Zhou, Thach Pham, Perry Grant, Seyed Ghetmiri, Aboozar Mosleh, Baohua Li, Jifeng Liu, Greg Sun, Richard Soref, John Tolle, Mansour Mortazavi, Shui-Qing Yu, “Si-based GeSn lasers with wavelength coverage of 2 to 3 μm and operating temperatures up to 180 K,” ACS Photonics, ACS Photonics, 2018, 5 (3), pp 827–833, DOI: 10.1021/acsphotonics.7b00938.
  3. Wei Dou, Mourad Benamara, Aboozar Mosleh, Joe Margetis, Perry Grant, Yiyin Zhou, Sattar Al-Kabi, Wei Du, John Tolle, Baohua Li, Mansour Mortazavi, Shui-Qing Yu, “Investigation of GeSn Strain Relaxation and Spontaneous Composition Gradient for Low-Defect and High-Sn Alloy Growth,” Scientific Reports  vol. 8, pp. 1-11, 2018.
  4. Huong Tran, Thach Pham, Wei Du, Yang Zhang, Perry C. Grant, Josh M. Grant, Greg sun, Richard A. Soref, Joe Margetis, John Tolle, Baohua Li, Mansour Mortazavi, and Shui-Qing Yu, “High performance Ge0.89Sn0.11 photodiode for low-cost shortwave infrared imaging,” Journal of Applied Physics 124, 013101 (2018); doi: 10.1063/1.5020510.
  5. T. A. Langdo, C. W. Leitz, M. T. Currie, E. A. Fitzgerald, A. Lochtefeld, and D. A. Antoniadis, “High quality Ge on Si by epitaxial necking”, Appl. Phys. Lett., 76, 3700 (2000).

 

KEYWORDS: SiGeSn; GeSn; CVD; emitters; detectors; Group IV photonics; silicon photonics; optoelectronic devices; monolithic integration; infrared imaging

US Flag An Official Website of the United States Government