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SiC Stress Tuning

Description:

OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Microelectronics OBJECTIVE: Mechanical stress tuning through Finite Element Analysis (FEA) modeling that can be used to predict silicon carbide (SiC) wafer warp/strength through processing steps such as power device fabrication, back grinding, stress relief processing, and backside metallization (BSM). DESCRIPTION: Stress engineering can be used for structural optimization of power devices, through mechanical stress tuning using FEA to predict stress [5] generated during the various manufacturing processes (dielectric deposition, metal deposition, wafer thinning, and BSM), which enables targeted reduction of stress in processing steps where large amounts of stress are to occur or reduction across multiple processing steps. Reduction of stress at interfaces improves device reliability performance, both in passive and active cycles [5] as well as, improving device yield [1]. Essentially, stress management and its optimization concurrently act as reliability improvement by means of reduction of overall stress, warpage, and a means of piezoresistive characteristics improvement [5]. An immediate effect of piezoresistivity is the change of device drain-source on-state resistance as adequate strain to the substrate is able to reduce Rdson, limiting dissipated power and temperature swing during operational life [5]. FEA has demonstrated the ability to predict wafer warp/strength for silicon (Si) through various fabrication processes. For front side device fabrication, FEA can be used to estimate the warping behavior of large thin coated wafers from the stress and strain in a thin film layer that is created as a result of either the deposition process or coefficient of thermal expansion (CTE)) mismatch [4]. The intrinsic stress is cause by non-equilibrium growth of the film microstructure, which will vary with the deposition process parameters and the thermal history post deposition [3]. To include front side device patterning in studies increases the complexity of the simulation beyond normal computational limits, but it is estimated that for conductive layers, the stress relief due to patterning is proportional to the area removed [4]. Wafer thinning is done to improve aid sawing operations, improve heat transfer within assemblies, reduce package height, and reduce Rdson [4]. Large warpage, usually as a result of backside processing, is one of the root causes of failures [4]. During wafer thinning, the substrate becomes more fragile, which increases the handling difficulties, as well as creates a potential source of defects that could propagate in subsequent processing steps [4]. As the wafer thickness is decreased during thinning, the wafer progressively become less able to support its own weight and resist the stresses generated by front side dielectric and metal deposition [4]. With a decrease in wafer thickness, the gravitational warp caused by the wafer weight also becomes significant and affects the simulation results if not accounted for [2]. Grinding induces intrinsic compressive stresses from texture disturbance in a subsurface layer [4], which is considered to be proportional to the diamond mesh or grit of the grinding wheel used for processing. Etching or other stress relief methods can be applied to in some cases to completely remove the stresses/subsurface damage caused by back grinding [4]. Lastly, the application of BSM, which acts as a thermal interface between die and package, a bonding layer between die and die attach material, or in some applications, as an electrical interface between die and package. Depending on metal stack materials and layer thickness used, significant wafer deflection can reduce metal adhesion reliability, which in turn, can cause peeling, lower reliability, and lower yield of packaged components. Most studies relate the stress in a film or substrate to the wafer curvature using the Stoney formula, but it has been shown to be inadequate for large deflections where large disagreement has been found [4] and ignores wafer hold mechanics (such as the vacuum holding chuck used in wafer thinning ) [2]. The Stoney formula is also not comprehensive enough to analyze wafer saddle shaped warpage (structures warped with compound curvature) [1]. Furthermore, for wafers of which thickness was reduced to less than 200microns, wafer warp became more severe and could be large in the elastic range or even beyond rendering the superposition method null to the calculation of the total warp [2]. Ultimately, the application of information learned from research on predictive modeling of silicon wafers could be combined and translated to build a parameterized system [2] that can be used by process engineers, without strong FEA knowledge, to examine and optimize both front side deposition, backside grind, and BSM processes used in the fabrication of high voltage SiC devices. The optimal solution will approach or exceed the following performance metrics: 1. Front side fabrication model/simulation shall include a device with up to two metal layers minimum a. For a given metal layer approximate surface area range of 10-50% must be shown b. Metal layers shall cover a thickness of 1000-3000Angstoms 2. Back grinding shall include at least two different grit sizes used in grinding wheels with diamond mesh sizes associated with fine grinding and coarse grinding a. Input for final (post thinning) thickness of substrate must include at minimum: 100um, 150um, 200um, 250um, and 300um 3. Wafers thinned to various thickness under the different grinding conditions represented in the study 4. BSM should include metal stacks of Ag/Au/Ni and Ti/Ni/Ag a. Two different metal thicknesses (on order of .1um to 5um) for each metal layer for each stack 5. Predicted results accurate to 5% 6. Able to receive input from user to flag/warn if stress or strength is not within acceptable limits provided by user PHASE I: Perform a feasibility study on the ability to utilize FEA or other computation means to predict the SiC wafer warpage and in turn, the residual stress in the wafer from power device fabrication, taking into account the effects of each processing step (front side deposition, backside grinding and BSM) and the processing parameters used during manufacturing. Develop a means in which engineers without FEA knowledge could input processing parameters for the aforementioned manufacturing steps to output a resultant warpage prediction and the associated residual stress. PHASE II: From the study prepared in Phase I, perform development of the prototype architecture of the predictive tool and experimental verification of the tool to predict warp and stress across a SiC wafer processed through front side fabrication, including deposition of dielectric materials and metals, back grinding, and BSM deposition. The performer is expected to show repeatability in the simulation performed and in the experiments performed as part of the verification of the tool, as well as deliver the testing data and the samples for which the experiments were executed. PHASE III DUAL USE APPLICATIONS: Predictive simulation tool or analysis capability can be marketed toward industry for commercial application and DoD for unique or low volume device manufacturing to use to support product design for cost and risk reduction as well as, design and reliability optimization. REFERENCES: 1. Mallik, Aditi & Stout, Roger. (2012). Simulation of Process-Stress Induced Warpage of Silicon Wafers Using ANSYS ® Finite Element Analysis. 43rd International Symposium on Microelectronics 2010, IMAPS 2010. 2010. 10.4071/isom-2010-WA1-Paper3. 2. Gao, Shang & Dong, Zhigang & Kang, Renke & Zhang, Bi & Guo, Dongming. (2014). Warping of Silicon Wafers Subjected to Back-grinding Process. Precision Engineering. 40. 10.1016/j.precisioneng.2014.10.009. 3. Irving, Scott & Liu, Youg. (2003). Wafer deposition/metallization and back grind, process-induced warpage simulation. 1459 - 1462. 10.1109/ECTC.2003.1216487. 4. Schicker, Johannes & Khan, Wasif & Arnold, Thomas & Hirschl, Christina. (2016). Simulating the Warping of Thin Coated Si Wafers Using Ansys Layered Shell Elements. Composite Structures. 140. 10.1016/j.compstruct.2015.12.062. 5. Calabretta, Michele & Sitta, Alessandro & Oliveri, Salvatore & Sequenzia, Gaetano. (2020). An Integrated Approach to Optimize Power Device Performances by Means of Stress Engineering. 10.1007/978-3-030-31154-4_41. 6. Wu, E., et al., "Influence of Grinding Process on Semiconductor Chip Strength", Proc 2002 Electronic Components and Technology Conference, San Diego, CA, May. 2002, pp. 1617-1621. KEYWORDS: Silicon carbide, Backside metal deposition, back grinding, stress engineering
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