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Low Cost, High Power, Opening and Closing Switches

Description:

OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Microelectronics, Directed Energy The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. OBJECTIVE: Develop low cost, high power, semiconductor opening switches (SOS), fast ionization dynistor (FID), or reverse switching dynistor (RSD) with an emphasis on being able to produce these devices at volume production facilities. DESCRIPTION: Semiconductor opening and closing switches (SOS, FID, and RSD) are used for a variety of pulsed power systems and high-power microwave (HPM) systems for providing high peak power and repetition rates [1, 2]. While silicon drift step recovery diodes (DSRD) have been demonstrated and produced in limited quantities over the past several years, the related devices have not [3]. The final product should be stackable in order to achieve higher voltage and current. The drawback with stacked devices are internal inductance, capacitance, and resistance increasing and creating unwanted effects on the circuit. Most recently, research has been done on wide bandgap materials which has shown higher performance [4, 5]. However, this topic will focus on single device performance and cost. Prototypes and tests will be done on both single device and stacked devices. The U.S. does not have a manufacturing source for many semiconductor opening and closing switches. Dopant concentration and junction depths are important factors for producing these devices. Preferably, proposed SOS, FID, or RSD devices can be produced in existing commercial semiconductor fabrication facilities without any additional capital costs. Ideally, the manufacturing process will be done on at least 6” substrates to facilitate volume production and with highly controllable process techniques without requiring near substrate melting point processing or multi-day processing steps, which is required for optimum silicon (Si) based DSRDs. Additionally, costs per device must be kept low in order to allow for broad adaptation. Silicon carbide (SiC) based DSRDs have been investigated and proven superior in performance to Si based DSRDs [6, 7]. For similar reasons, SiC based SOS, FID, and RSD devices are of interest [8]. However, SiC substrates are known to be much more expensive compared to Si substrates and may impact the total cost for the device. Cost vs. performance tradeoffs will be considered. Ideal minimum single device characteristics for an opening switch: 1. Breakdown voltage: >800V with full width at half maximum (FWHM) <1 ns or >600V with FWHM <5 ns 2. Peak Repetitive Operating current: 25 A / mm^3 3. Pulse repetition frequency: 100 kHz (static) to (1 MHz) dynamic 4. Switching time (transition or snap time): <1 ns for 80ns or <3.5 ns for 200ns of pumping time 5. Differential voltage (-dV/dt): 2kV/ns 6. Stackable design with low resistance loss 7. Form factor: circular with a diameter of 0.25”-0.8” 8. Cost: ≤ $100 per single device or ≤ $2,040 per delivered stack with 10kV of breakdown voltage a. If in a stacked form factor, the added cost for stacking multiple individual devices to form a stack does not increase the final deliverable stack cost by more than 20%. An example 10kV stack might require 17 devices (10kV divided by 600V); however, it should cost no more than $2,040 delivered (17 devices multiplied by $100 increased by 20%). Ideal minimum single device characteristics for a closing switch: 1. Breakdown voltage: >4kV static (1 second) and >6kV dynamic with 5 ns FWHM input 2. Pulse repetition frequency: 100 kHz (static) to (1 MHz) dynamic 3. Switching time (turn on time): <1 ns 4. Differential voltage (-dV/dt): 4-6kV/ns 5. Stackable design with low loss 6. Form factor: circular with a diameter of 0.25”-0.8” 7. Cost: ≤ $100 per single device, if in a stacked form factor, the added cost for stacking does not increase the final deliverable device by 20%. See the example in the opening switch section above. DIRECT TO PHASE II: DMEA will only accept Direct to Phase II proposals. PHASE I: Perform a feasibility study on designing, modeling, manufacturing, and characterizing one of the following types of devices: SOS, FID, or RSD. The end result of Phase I is a feasibility study report justifying the rationale supporting the proposed device and manufacturing process. Additionally, depending on the material used, high power devices can generate a lot of heat that can easily degrade the lifespan or performance of a device and thermal management can become an issue. Respondents should include a plan to evaluate and mitigate heat generation. Thermal management can be mitigated by material selection, but respondents must investigate and address this as part of the feasibility study report. Ideal minimum device characteristics allows proposals an opportunity to balance cost vs. performance. The report will explicitly address the following items: 1. The feasibility study shall state which proposed device will be produced and whether it is intended as an opening or closing switch. 2. The feasibility study shall describe modeled characteristics and performance along with relevant figures, equations, and input parameters. It must include: a. Breakdown voltage (static and dynamic) b. Peak repetitive operating current c. Pulse repetition frequency d. Switching time e. Differential voltage (-dV/dt) f. Differential current (dI/dt) g. Temperature range (storage range and operating range) h. Form factor size and shape i. Number of devices needed to be stacked together to reach a dynamic breakdown voltage of 10kV along with performance characteristics of a 10kV stack j. Max number of stacked devices before thermal management is required, as well as the analysis that supports this conclusion 3. The feasibility study shall detail the process and techniques used along with associated costs. If there are bulk quantity discounts factored in, the report shall disclose quantity price break points and which steps were discounted where relevant. It is acceptable if proposed initial cost is higher than ideal; however, the proposal must detail a viable plan to scale costs to a competitive rate along with the order quantities required in order to achieve price break. It must include: a. Proposed manufacturing process flow and techniques used, including dicing, stacking, and packaging methodologies b. Bulk material and specification (i.e., crystal orientation, dopant species, resistivity, thicknesses, etc.) c. Cost break down for manufacturing comparison versus existing (both commercial and research) and comparative theoretical options. Table format preferred. d. Methodologies and analysis techniques used for characterizing the proposed device (i.e., junction depth, doping profile, electrical performance, etc.) e. Thermal management solutions for heat generated if or when thermal management is required The delivered report must fully describe the proposed techniques and characterization methodologies, including a notional list of fabrication tools, facility requirements, and a program plan for follow-on phase development. The report must describe the tradeoff considerations done to meet cost and minimum device specs. If any of the above items cannot be fully addressed, the report must include relevant research and rationale that demonstrates their inapplicability to the proposed technique. If adhering to the above items is possible, but not financially feasible, the report must include relevant justification. FEASIBILITY DOCUMENTATION: Offerors interested in participating in Direct to Phase II must include in their response to this topic, Phase I feasibility documentation that substantiates the scientific and technical merit and Phase I feasibility described in Phase I above has been met (i.e., the small business must have performed Phase I-type research and development related to the topic, but from non-SBIR funding sources) and describes the potential commercialization applications. The documentation provided must validate that the proposer has completed development of technology as stated in Phase I above. Documentation should include all relevant information including, but not limited to: technical reports, test data, prototype designs/models, and performance goals/results. Work submitted within the feasibility documentation must have been substantially performed by the offeror and/or the principal investigator (PI). PHASE II: Based on the aforementioned study and applicable development/innovation, Phase II will result in producing fully functioning prototypes of either a SOS, FID, or RSD device as described in Phase I. Test and deliver the prototype, characterization results, all generated files (i.e., process recipes, process specifications, etc.), operating instructions, and test plans to the Government for further testing and verification. If the prototype does not meet the minimum requirements listed as described in Phase I, rationale must be provided for each parameter specification not met and a remediation strategy must be presented. Required Phase II deliverables must include: 1. Validated characterization results verifying that ten (10) single device form factor prototype devices met the specifications as described in Phase I. 2. Validated characterization results demonstrating the performance of five (5) stacked devices. Each stack must reach a dynamic breakdown voltage of 10kV. Stacked device performance and characteristics results shall be reported in a similar format as the single device form factor. 3. At least fifty (50) untested, unpackaged, single device form factor samples and at least ten (10) untested, unpackaged, pre-diced wafers for further testing and validation. The final report must reflect that the tested prototypes were selected from across multiple lots to demonstrate repeatability and quality with low variation within wafer, wafer to wafer, and lot to lot. If a non-random selection was required to optimize performance, the final report must detail reasoning for using non-random selection and the selection criteria used. Deliver a detailed final report that documents the cost breakdown per single form factor, cost breakdown per stacked device, manufacturing processes utilized, fabrication toolset required to perform the proposed techniques, all facility requirements, all electrical characterization and device design data (TCAD files, modeling/simulation, etc.), and diffusion profile results (i.e,. SRP). If there are bulk quantity discounts factored in any of the cost breakdowns, the final report shall disclose quantity price break points and which steps were discounted where relevant. The final report shall contain sufficient technical detail such that an entity skilled in semiconductor fabrication can repeat the presented results to the same level of performance. PHASE III DUAL USE APPLICATIONS: There may be opportunities for further development of semiconductor opening and closing switches for use in a specific military or commercial application. During Phase III, offerors may refine the performance of the design and produce pre-production quantities for evaluation by the Government. Semiconductor opening and closing switches have commercial and Government applications. Pulsed power application examples include electron accelerators, X-ray pulse devices, high-power microwave electronics, pumping of gas lasers, ignition of electrical discharges, engine ignition, and ion implantation [9, 10]. REFERENCES: 1. Pang L, Zhang Q, Ren B, He K. A compact repetitive high-voltage nanosecond pulse generator for the application of gas discharge. Rev Sci Instrum. 2011 Apr;82(4):043504. doi: 10.1063/1.3572265. PMID: 21529005. 2. S. Schneider and T. F. Podlesak, "Reverse switching dynistor pulsers," Digest of Technical Papers. 12th IEEE International Pulsed Power Conference. (Cat. No.99CH36358), 1999, pp. 214-218 vol.1, doi: 10.1109/PPC.1999.825450. 3. F. Arntz, M. Gaudreau, M. Kempkes, D. Technologies, A. Krasnykh and A. Kardo-Sysoev, "A kicker driver for the international linear collider," 2007 IEEE Particle Accelerator Conference (PAC), 2007, pp. 2972-2974, doi: 10.1109/PAC.2007.4440638. 4. Y. Yang, L. Liang, H. Shang, Y. Kang and H. Yan, "Design of Press-Pack Packaging for High Voltage SiC DSRD Stack," 2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia), 2020, pp. 1-4, doi: 10.1109/WiPDAAsia49671.2020.9360250. 5. Yan X, Liang L, Huang X, Zhong H, Yang Z. 4H-SiC Drift Step Recovery Diode with Super Junction for Hard Recovery. Materials. 2021; 14(3):684. https://doi.org/10.3390/ma14030684. 6. R. Sun et al., "10-kV 4H-SiC Drift Step Recovery Diodes (DSRDs) for Compact High-repetition Rate Nanosecond HV Pulse Generator," 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2020, pp. 62-65, doi: 10.1109/ISPSD46842.2020.9170132. 7. Yan X, Liang L, Huang X, Zhong H, Yang Z. 4H-SiC Drift Step Recovery Diode with Super Junction for Hard Recovery. Materials (Basel). 2021 Feb 2;14(3):684. doi: 10.3390/ma14030684. PMID: 33540734; PMCID: PMC7867219. 8. Igor V. Grekhov, Pavel A. Ivanov, Dmitry V. Khristyuk, Andrey O. Konstantinov, Sergey V. Korotkov, Tat’yana P. Samsonova, “Sub-nanosecond semiconductor opening switches based on 4H–SiC p+pon+-diodes,” Solid-State Electronics, Volume 47, Issue 10, 2003, Pages 1769-1774, ISSN 0038-1101, https://doi.org/10.1016/S0038-1101(03)00157-6. 9. S. N. Rukin , "Pulsed power technology based on semiconductor opening switches: A review", Review of Scientific Instruments 91, 011501 (2020) https://doi.org/10.1063/1.5128297. 10. H. Akiyama, T. Sakugawa, T. Namihira, K. Takaki, Y. Minamitani and N. Shimomura, "Industrial Applications of Pulsed Power Technology," in IEEE Transactions on Dielectrics and Electrical Insulation, vol. 14, no. 5, pp. 1051-1064, October 2007, doi: 10.1109/TDEI.2007.4339465. 11. X. Huang, L. Liang, G. Wang, Z. Qing, “Failure case studies of fast ionization dynistors,” in Microelectronics Reliability, Volume 126, 2021, 114257, ISSN 0026-2714, doi: 10.1016/j.microrel.2021.114257. 12. I. V. Grekhov, S. V. Korotkov, A. L. Stepaniants, D. V. Khristyuk, V. B. Voronkov and Y. V. Aristov, "High-power semiconductor-based nano and subnanosecond pulse Generator with a low delay time," in IEEE Transactions on Plasma Science, vol. 33, no. 4, pp. 1240-1244, Aug. 2005, doi: 10.1109/TPS.2005.852349. KEYWORDS: Drift Step Recovery Diode, DSRD, Semiconductor Opening Switch, SOS, Fast Ionization Dynistor, FID, Reverse Switching Dynistor, RSD, Pulse Repetition Frequency, PRF; High Power Microwave, HPM, Solid State, Ultra-Wideband, UWB.
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