You are here

SBIR Phase I:Efficient Arithmetic on Quasi-Compressed Data for Performance Improvement

Award Information
Agency: National Science Foundation
Branch: N/A
Contract: 2111696
Agency Tracking Number: 2111696
Amount: $256,000.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: IT
Solicitation Number: NSF 20-527
Timeline
Solicitation Year: 2020
Award Year: 2022
Award Start Date (Proposal Award Date): 2022-02-01
Award End Date (Contract End Date): 2023-10-31
Small Business Information
3913 BIBBITS DR
EAST PALO ALTO, CA 94303
United States
DUNS: 117672636
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 David Chen
 (408) 439-0412
 Dave.h.chen@gmail.com
Business Contact
 David Chen
Phone: (408) 439-0412
Email: Dave.h.chen@gmail.com
Research Institution
N/A
Abstract

The broader impact of this Small Business Innovation Research (SBIR) Phase I project is to improve the performance of semiconductor chips.Specifically, it develops a novel method to operate directly on compressed data, saving time, energy, and latency.This improved performance will affect computationally intensive applications such as medical imaging (e.g., CT/MRI), climate simulation, hurricane warnings, and earthquake alerts.This Small Business Innovation Research (SBIR) Phase I project develops a method to operate on compressed data. Today, computers apply data compression to identify and remove redundancy in the data in order to save storage space.Computers apply arithmetic to compute in integers or real numbers (usually represented internally as floating-point data).However, today's computers first decompress the data, compute, and then compress the computed result, consuming additional time and energy.This project develops an arithmetic and math hardware accelerator capable of processing compressed data directly to dramatically improve computation performance, storage effectiveness, and energy efficiency.This project combines data compression and floating-point engineering to deliver the first-ever Compressed Floating-Point Unit (CFPU) that minimizes semiconductor and energy usage and reduces computation latency.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

* Information listed above is at the time of submission. *

US Flag An Official Website of the United States Government