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High-Performance Space Computing Technology

Description:

Scope Title:

Time-Sensitive Networking (TSN) and Time-Triggered Ethernet (TTE)

Scope Description:

Create a proof-of-concept fault-tolerant network leveraging open standards like Ethernet, Time-Sensitive Networking (TSN), Time-Triggered Ethernet (TTE), and remote direct memory access (RDMA) over Converged Ethernet (RoCE) that supports:

  • Processor clustering.
  • Time synchronization.
    • Relative synchronization.
    • Interoperability with multiple synchronization domain.
  • Fault tolerance.
    • Omission failure tolerant.
    • Multiple device failure tolerant (e.g., simultaneous end system and switch failure).
    • Transparent and bounded-time failure recovery.
  • Bounded traversal time.
  • Compatible with heterogenous networks.
  • Ability for low-cost noncritical devices to synchronize without specialized hardware (e.g., TSN network interface card (NIC)), allowing the possibility for a software implementation.
  • Guaranteed formal correctness or a clear path for formal verification.
    • Formal proofs for key properties:
      • Self-stabilization
      • Cold start
      • Integration
      • Clique detection

Expected TRL or TRL Range at completion of the Project: 1 to 4

Primary Technology Taxonomy:

  • Level 1 02 Flight Computing and Avionics
  • Level 2 02.X Other Flight Computing and Avionics

Desired Deliverables of Phase I and Phase II:

  • Analysis
  • Prototype
  • Hardware
  • Software
  • Research

Desired Deliverables Description:

Phase I Deliverables:

For software and hardware elements, a solid conceptual design, plan for full-scale prototyping, and simulations and testing results to justify prototyping approach. Detailed specifications for intended Phase II deliverables.

Phase II Deliverables:

For software and hardware elements, a prototype that demonstrates sufficient performance and capability and is ready for future development and commercialization.

State of the Art and Critical Gaps:

Most NASA missions utilize processors with in-space-qualifiable high-performance computing that has high power dissipation (approximately 18 W), and the current state-of-practice Technology Readiness Level 9 (TRL-9) space computing solutions have relatively low performance (between 2 and 200 DMIPS (Dhrystone million instructions per second) at 100 MHz). A recently developed radiation-hardened processor provides 5.6 GOPS (giga operations per second) performance with a power dissipation of 17 W. Neither of these systems provides the desired performance, power-to-performance ratio, or flexibility in configuration, performance, power management, fault tolerance, or extensibility with respect to heterogeneous processor elements. Onboard network standards exist that can provide >10 Gbps bandwidth, but not everything is available to fully implement them.

Relevance / Science Traceability:

The high-performance spaceflight computing (HPSC) ecosystem is enhancing to most major programs in the Exploration Systems Development Mission Directorate (ESDMD) and the Space Operations Mission Directorate (SOMD). It is also enabling for key Space Technology Mission Directorate (STMD) technologies that are needed by ESDMD-SOMD. Within the Science Mission Directorate (SMD), strong mission pull exists to enable onboard autonomy across Earth science, astrophysics, heliophysics, and planetary science missions. There is also relevance to other high-bandwidth processing applications within SMD, including adaptive optics for astrophysics missions and science data reduction for hyperspectral Earth science missions. 

References:

  • RISC-V: https://riscv.org/news/2019/09/risc-v-gains-momentum-as-industry-demands-custom-processors-for-new-innovative-workloads/
  • Next Generation Space Interconnect Standard: http://www.rapidio.org/wp-content/uploads/2014/10/RapidIO-NGSIS-Seminar-July-23-2014.pdf
  • He, J., et al. Provably Correct Systems. Formal Techniques in Real-Time and Fault-Tolerant Systems. pp. 288-335. ProCoS. 1994.
  • Reis, G.A. SWIFT: Software Implemented Fault Tolerance. International Symposium on Code Generation and Optimization. IEEE. 2004.
  • Wessman, N., et al. De-RISC: The First RISC-V Space-Grade Platform for Safety-Critical Systems. pp. 17-26. IEEE Space Computing Conference Proceedings. 2021.
  • Franconi, N., et al. Signal and Power Integrity Design Methodology for High-Performance Flight Computing Systems. pp. 17-26. IEEE Space Computing Conference Proceedings. 2021.
  • Yanguas-Gil, A., et al. Neuromorphic Architectures for Edge Computing under Extreme Environments. pp. 39-45. IEEE Space Computing Conference Proceedings. 2021.
  • Sabogal, S., et al. A Methodology for Evaluating and Analyzing FPGA-Accelerated, Deep-Learning Applications for Onboard Space Processing. pp. 143-154. IEEE Space Computing Conference Proceedings. 2021.

Scope Title:

Coprocessors for Digital Signal Processing (DSP) and Artificial Intelligence (AI)

Scope Description:

Create a proof-of-concept (POC) end-to-end software/firmware/field-programmable gate array (FPGA) bitstream stack using an open-source framework (like OpenCL) to enable heterogeneous compute offload for space-grade processors. Coprocessors to (a) accelerate onboard AI applications or (b) perform DSP functions. Specifically, technologies are sought that either enable the reliable use of commercial off-the-shelf (COTS) coprocessors in space systems, or fault-tolerant internet protocol (IP) cores that can be implemented in a radiation-hardened FPGA. Preferred processor interface is Compute Express Link (CXL) or, alternatively, Peripheral Component Interconnect Express (PCIe).

Expected TRL or TRL Range at completion of the Project: 1 to 4

Primary Technology Taxonomy:

  • Level 1 02 Flight Computing and Avionics
  • Level 2 02.1 Avionics Component Technologies

Desired Deliverables of Phase I and Phase II:

  • Research
  • Analysis
  • Prototype
  • Hardware
  • Software

Desired Deliverables Description:

Phase I Deliverables:

For software and hardware elements, a solid conceptual design, plan for full-scale prototyping, and simulations and testing results to justify prototyping approach. Detailed specifications for intended Phase II deliverables.

Phase II Deliverables:

For software and hardware elements, a prototype that demonstrates sufficient performance and capability and is ready for future development and commercialization.

State of the Art and Critical Gaps:

Commercial AI coprocessor devices exist, but with unknown radiation performance and applicability to NASA onboard processing tasks.

Relevance / Science Traceability:

The high-performance spaceflight computing (HPSC) ecosystem is enhancing to most major programs in the Exploration Systems Development Mission Directorate (ESDMD) and the Space Operations Mission Directorate (SOMD). It is also enabling for key Space Technology Mission Directorate (STMD) technologies that are needed by ESDMD-SOMD. Within the Science Mission Directorate (SMD), strong mission pull exists to enable onboard autonomy across Earth science, astrophysics, heliophysics, and planetary science missions. There is also relevance to other high-bandwidth processing applications within SMD, including adaptive optics for astrophysics missions and science data reduction for hyperspectral Earth science missions. 

References:

Possible existing open-source projects for consideration, in order of relevance:

Alternately, license a GPU, TPU, or DSP core from a vendor and prototype it in the FPGA:

 

Experience of Qualcomm enabling code generation for their Hexagon DSP with LLVM: https://www.llvm.org/devmtg/2011-11/Simpson_PortingLLVMToADSP.pdf

Scope Title:

Solid-State Memory Drives

Scope Description:

Proof-of-concept of nonvolatile storage systems extending industrial and enterprise solid-state drives for space applications targeting the following capabilities:  

  • High reliability.
  • Space-radiation tolerant.
  • Space-temperature tolerant (especially extreme cold).
  • Endure the high shock/vibration environments of space launch.

Concept must have a minimum of 1-TB capacity with a targeted transfer rate of 1,500 MB/s. Concept should leverage industry standard interfaces like Peripheral Component Interconnect Express (PCIe) or Ethernet and be compliant with NVM Express (NVMe) software stack. 

Expected TRL or TRL Range at completion of the Project: 1 to 4

Primary Technology Taxonomy:

  • Level 1 02 Flight Computing and Avionics
  • Level 2 02.2 Avionics Systems and Subsystems

Desired Deliverables of Phase I and Phase II:

  • Research
  • Analysis
  • Prototype
  • Hardware

Desired Deliverables Description:

Phase I Deliverables:

For software and hardware elements, a solid conceptual design, plan for full-scale prototyping, and simulations and testing results to justify prototyping approach. Detailed specifications for intended Phase II deliverables.

Phase II Deliverables:

For software and hardware elements, a prototype that demonstrates sufficient performance and capability and is ready for future development and commercialization.

State of the Art and Critical Gaps:

Radiation-hardened memories lack capacity and/or performance, while COTS-based memories are susceptible to radiation-induced upsets.

Relevance / Science Traceability:

The high-performance spaceflight computing (HPSC) ecosystem is enhancing to most major programs in the Exploration Systems Development Mission Directorate (ESDMD) and Space Operations Mission Directorate (SOMD). It is also enabling for key Space Technology Mission Directorate (STMD) technologies that are needed by ESDMD-SOMD. Within the Science Mission Directorate (SMD), strong mission pull exists to enable onboard autonomy across Earth science, astrophysics, heliophysics, and planetary science missions. There is also relevance to other high-bandwidth processing applications within SMD, including adaptive optics for astrophysics missions and science data reduction for hyperspectral Earth science missions. 

References:

  • RISC-V: https://riscv.org/news/2019/09/risc-v-gains-momentum-as-industry-demands-custom-processors-for-new-innovative-workloads/
  • Next Generation Space Interconnect Standard: http://www.rapidio.org/wp-content/uploads/2014/10/RapidIO-NGSIS-Seminar-July-23-2014.pdf
  • He, J., et al. Provably Correct Systems. Formal Techniques in Real-Time and Fault-Tolerant Systems. pp. 288-335. ProCoS. 1994.
  • Reis, G.A. SWIFT: Software Implemented Fault Tolerance. International Symposium on Code Generation and Optimization. IEEE. 2004.
  • Wessman, N., et al. De-RISC: The First RISC-V Space-Grade Platform for Safety-Critical Systems. pp. 17-26. IEEE Space Computing Conference Proceedings. 2021.
  • Franconi, N., et al. Signal and Power Integrity Design Methodology for High-Performance Flight Computing Systems. pp. 17-26. IEEE Space Computing Conference Proceedings. 2021.
  • Yanguas-Gil, A., et al. Neuromorphic Architectures for Edge Computing under Extreme Environments. pp. 39-45. IEEE Space Computing Conference Proceedings. 2021.
  • Sabogal, S., et al. A Methodology for Evaluating and Analyzing FPGA-Accelerated, Deep-Learning Applications for Onboard Space Processing. pp. 143-154. IEEE Space Computing Conference Proceedings. 2021.

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