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Readout Integrated Circuit Development for 2-micron Cutoff Linear Mode Staircase Avalanche Photodiodes

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OUSD (R&E) MODERNIZATION PRIORITY: Microelectronics TECHNOLOGY AREA(S): Sensors The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. OBJECTIVE: Design, model, and fabricate a readout integrated circuit specifically tailored for high-gain linear mode staircase avalanche photodiodes that operate at 2 µm cutoff, high frame rates, and thermoelectric cooling compatible temperatures DESCRIPTION: Avalanche photodiodes (APDs) are photodiodes with an internal gain mechanism that exploit the photoelectric effect to convert a single photon to multiple electrons. Functionally, they are the semiconductor analog of photomultipliers. APDs use a high reverse bias voltage to create a strong internal electric field that accelerates electrons (or holes) created by the absorption of incident photons through the crystal lattice to produce secondary electrons (holes) by impact ionization. APDs have been widely deployed for use in telecommunications, military, and research applications for imaging, single photon detection, and ranging. Linear mode staircase APDs are a particular design proposed by Capasso [1] in the early 1980s that theorized a device that incorporated both energetic and spatial determinicity in the gain resulting in gains of 2N where N is the number of steps in the staircase. Attempts to meet the performance gains projected have continued, [2,3] in particular, recent advances in in the Gain Enhancement by Novel Impact Ionization (GENII) program have resulted in demonstrations of high gain (>1000), high operating temperature (>240K), and low excess noise factor (<1.1) at modest dark current (<10 µA/cm2) at the pixel level with an innovative AlInAsSb-based digital alloy staircase APD structure with a per-step gain near the theoretical limit of two [4]. In order to demonstrate the military relevance and further advance the technology and manufacturing readiness levels (TRL and MRL), a custom readout integrated circuit (ROIC) must be designed, fabricated, and tested with the staircase APD structures. Likewise, read-out integrated circuits have been developed for linear-mode APDs [5-7]. State of the art APD ROICs have larger pixel pitch (~100 microns or more) and require higher voltages to operate. It is desirable for the ROIC to operate at low voltage and be designed for smaller pixel pitches and still achieve SOA performance. The overall technical objectives of this topic are to produce a staircase APD ROIC that can meet the metrics laid out in Table 1. Metric Goal Array size 32 x 32 Pixel Pitch (µm) <50 Frame rate (kHz) >10 Op. Temp (K) 240 Dynamic Range (bits) 16 Range Resolution (cm) <30 Power (W) 0.5 Dark Current (µA/cm2) 10 Excess noise factor <1.1 PHASE I: As this is a Direct to Phase II (DP2) solicitation, Phase I proposals will not be accepted or reviewed. In order to qualify for DP2, proposers must provide documentation to substantiate the following: • Proposer has previously demonstrated their ability to design, fabricate, and test APD ROICs (e.g. sample data from prior APD ROIC efforts) • Proposer has preliminary performance models for a 32x32 staircase APD array that meets the metrics detailed in Table 1 • Proposer should have detector results that demonstrate APD behavior (e.g., published paper or third-party test results) PHASE II: For the base Direct to Phase II effort, the proposer shall develop: • Detailed design ready for tape-out of linear mode APD ROIC able to meet the metrics detailed in Table 1 • Detailed simulated performance for 32 x 32 staircase APD array i. Schedule/Milestones/Deliverables Phase Month Milestone Base Phase 2 1 Kickoff meeting. The kickoff meeting should identify the detailed technical approach, preliminary expected performance, detailed specifications, detailed program schedule, anticipated risks and corresponding mitigation approach(es), level of effort and key personnel required, and any anticipated follow up actions. 3 Update report. A report and corresponding meeting to present an update on architecture trades and progress towards detailed requirements. 5 Requirements review. A report and corresponding meeting to present the detailed system requirements review (SRR). 7 Update report. A report and corresponding meeting to present an update progress towards preliminary design. 9 Preliminary design. A report and corresponding meeting for preliminary design review (PDR). Initial FPA performance estimates, pixel level layouts, and details of each layer proposed in the ROIC shall be provided. 11 Update report. A report and corresponding meeting to present an update progress towards block level review. 13 Block level review. A report and corresponding meeting for block level review. Pixel level schematics and variations as well as top level periphery approach shall be provided. 17 Critical design. A report and corresponding meeting for critical design review (CDR). All elements required to bring the ROIC design to tapeout shall be provided. 18 Final Report. A report detailing all technical progress made in the base effort. PHASE III DUAL USE APPLICATIONS: (U) Phase III efforts will demonstrate a fully packaged camera composed of high operating temperature, linear mode staircase APDs. Potential commercial applications include single-photon detection, ranging, and imaging. REFERENCES: 1. F. Capasso and W. T. Tsang, "Superlattice, graded band gap, channeling and staircase avalanche photodiodes towards a solid-state photomultiplier," 1982 International Electron Devices Meeting, 1982, pp. 334-337, doi: 10.1109/IEDM.1982.190288. 2. R. S. Fyath and J. J. O'Reilly, "Effect on the performance of staircase APDs of electron impact ionization within the graded-gap region," in IEEE Transactions on Electron Devices, vol. 35, no. 8, pp. 1357-1363, Aug. 1988, doi: 10.1109/16.2559. 3. G. M. Williams, M. Compton, D. A. Ramirez, M. M. Hayat and A. S. Huntington, "Multi-Gain-Stage InGaAs Avalanche Photodiode With Enhanced Gain and Reduced Excess Noise," in IEEE Journal of the Electron Devices Society, vol. 1, no. 2, pp. 54-65, Feb. 2013, doi: 10.1109/JEDS.2013.2258072. 4. S.D. March, A.H. Jones, A.J. Muhowski, S.J. Maddox, M. Ren, S.R. Bank, “Digital Alloy Staircase Avalanche Photodetectors with Tunneling-Enhanced Gain”, IEEE Journal of Selected Topics in Quantum Electronics, 28, 3803513 (2022). 5. J. Asbrock, S. Bailey, D. Baley, J. Boisvert, G. Chapman, G. Crawford, T. de Lyon, B. Drafahl, J. Edwards, E. Herrin, C. Hoyt, M. Jack, R. Kvaas, K. Liu, W. McKeag, R. Rajavel, V. Randall, S. Rengarajan, J. Riker, "Ultra-High sensitivity APD based 3D LADAR sensors: linear mode photon counting LADAR camera for the Ultra-Sensitive Detector program," Proc. SPIE 6940, Infrared Technology and Applications XXXIV, 69402O (5 May 2008). 6. J.D. Beck, R. Scritchfield, P. Mitra, W. Sullivan III, A.D. Gleckler, R. Strittmatter, R.J. Martin, "Linear-mode photon counting with the noiseless gain HgCdTe e-APD," Proc. SPIE 8033, Advanced Photon Counting Techniques V, 80330N (13 May 2011). 7. W. Sullivan III, J. Beck, R. Scritchfield, M. Skokan, P. Mitra, X. Sun, J. Abshire, D. Carpenter, B. Lane, "Linear mode photon counting from visible to MWIR with HgCdTe avalanche photodiode focal plane arrays," Proc. SPIE 9492, Advanced Photon Counting Techniques IX, 94920T (13 May 2015). KEYWORDS: Photodiode, photodetector, staircase avalanche photodiode, readout integrated circuit
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