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Ontology-Based Electronic Design Automation (EDA) Tools

Description:

OUSD (R&E) MODERNIZATION PRIORITY: Artificial Intelligence/ Machine Learning, Autonomy, Cybersecurity, Microelectronics, Networked Command, Control and Communications (C3), Space TECHNOLOGY AREA(S): Information Systems, Sensors OBJECTIVE: Integrate ontology-based application analysis techniques into EDA tools in order to generate efficient hardware description language (HDL) from C/C++ code in days instead of months. DESCRIPTION: FPGAs and ASICs can now be used to implement entire systems on a chip (SoCs), using heterogeneous components such as CPUs, GPUs, accelerators, memories, and specialized IP blocks. Current EDA tools, such as VHDL, Verilog, Chisel, are challenging to use compared with high-level coding languages, and the programming of different applications onto compute hardware, such as FPGAs or ASICs, can take months to years. This challenge is compounded by the increasing complexity of the target device, the requirement to execute multiple application tasks simultaneously, and the need to adapt flexibly to changing circumstances and requirements. To begin to address this challenge, the DARPA Domain-Specific System on a Chip (DSSoC) program has begun to develop approaches to improve functionality, productivity and flexibility in the development of SoCs aimed at domains of applications, such as communication, signal processing or autonomous vehicles. In the early 2000s there were attempts to analyze processing specialization by classifying programs into a taxonomy. An attempt from 2004 came up with a list of seven classes, or motifs, of programs in high performance computing. The Berkeley view of this in 20061 referred to these as the “Seven Dwarfs” and then went on to expand this list to thirteen. Later, another taxonomy was developed for the seven dwarfs of symbolic computation2. Taxonomies are useful but have limitations as they only provide a list of categories and not relationships between categories. DSSoC is focusing on extending the taxonomy concept into ontologies for the domains by developing ontology tools for the analysis of application code, and by automating the generation of executable images for compute hardware (accelerators, FPGAs and ASICs) from C/C++. These new ontology-based techniques can be used to perform deep analysis of the entire body of application code, identifying loops, kernels, primitives, and mathematical functions that can be mapped to accelerators, special-purpose hardware for Artificial Intelligence (AI), Digital Signal Processing (DSP), and other hard IP blocks. Such accelerators and IP blocks will be specific to the target device. Knowledge-based rules and AI-based solution methods can be used to optimize the incorporation of accelerators into the design and the generation of HDL from C/C++, and to meet the application and target device timing, area, and power constraints. The entire ETA tool stack should be user-friendly and as automated as far as possible, for high productivity, including application code inputs, simulation and profiling, debugging, and run-time scheduling of compute and memory resources. The goal of this SBIR is to closely integrate ontology-based application analysis techniques into EDA tools in order to generate efficient hardware description language (HDL) from C/C++ code in days instead of months. The resulting environment would be capable of analyzing the body of code associated with the target application domain and identifying the compute-intensive portions to be mapped to accelerators; automatically generating HDL from the C/C++ code for the target device, including accelerator IP as needed and optimizing the design to meet application requirements and constraints; and using the application/ontology knowledge to automate the run-time scheduling of resources and data management. PHASE I: The DSSoC program demonstrated that ontology-based application analysis can be used to identify the compute-intensive portions (loops, kernels, primitives, functions) of a set of applications, and can feed this information to software tools, such as code generators, accelerator designs, and run-time libraries. In order to establish Phase I feasibility, the proposer should provide documentation based on using an ontology-based analysis approach to inform EDA tools in the automated generation of Verilog or VHDL for an FPGA. Proposers interested in submitting a Direct to Phase II (DP2) proposal must provide documentation to substantiate that the scientific and technical merit and feasibility described above has been met and describes the potential commercial applications. Documentation should include all relevant information including, but not limited to: technical reports, test data, prototype designs/models, and performance goals/results. For detailed information on DP2 requirements and eligibility, Appendix A of the DARPA 2022.4 Instructions. PHASE II: The goal of this SBIR is to develop or adapt a set of EDA tools that incorporate the ontology-based analysis research from DSSoC to auto-generate optimized HDL from C/C++ for a target FPGA, ASIC, or heterogeneous platform. The generated code should be nearly as good as human-optimized code, but productivity should be much higher: The performance penalty for using the ontology-based automated tools versus hand-coding should be no greater than 5%, and the productivity boost should be at least 50X. At the end of Phase II the proposer will demonstrate an end-to-end set of EDA tools that take C/C++ application code (plus other inputs such as constraints and descriptions of available accelerators and other IP) and generate high-performance HDL to execute on an FPGA, ASIC, or heterogeneous compute platform. Schedule/Milestones/Deliverables • Month 2: Technical Approach Report, that identifies additions and modifications that will be researched, developed, and customized for incorporation in the pilot demonstration. • Month 4: PI meeting, including demonstration of progress to date, PowerPoint presentations of accomplishments and plans. • Month 6: Demonstration Plan that identifies schedule, location, computing resources, and any other requirements for the pilot demonstration. • Month 8: PI meeting, including demonstration of progress to date, PowerPoint presentations of accomplishments and plans; identification of potential transition partner(s) and other interested DoD organizations. • Month 10: EDA tool delivery, including Software licenses valid for a year, for operation by DARPA or other Government personnel for additional demonstrations, with suitable documentation in a contractor proposed format. • Month 12: Final report, including quantitative metrics on application performance (should be at least 95% as measured by clock speed, device area, and power consumption) and productivity gains (should be at least 50X as measured by development engineer-hours) compared with hand-coding for the pilot demonstration. Proposal for Phase II option, such as new target hardware and/or domain-specific functionality. The report shall also document any scientific advances that have been achieved under the program. (A brief statement of claims supplemented by publication material will meet this requirement.) Final PI meeting presentation material. Phase II Option Based on progress and status during the Phase II (base), Phase II option activities could include: improved levels of automation, such as productivity improvements to 100X compared with hand-coding; improved levels of optimization, such as run-time performance exceeding hand-coded applications; and expanding the range of targets to include additional devices, such as additional FPGA manufacturers or device families. Schedule/Milestones/Deliverables • Month 1: Technical Approach Report, that outlines details of approach for improved levels of automation, new target hardware and/or domain-specific functionality and demonstration plan that identifies schedule, location, computing resources, and any other requirements for the enhanced pilot demonstration • Month 3: PI meeting, including demonstration of progress to date, PowerPoint presentations of accomplishments and plans and identification of potential transition partner(s) and other interested DoD organizations. • Month 5: Enhanced EDA tool delivery, including Software licenses valid for a year, for operation by DARPA or other Government personnel for additional demonstrations, with suitable documentation in a contractor proposed format. • Month 6: Final report, including quantitative metrics on application performance (should be greater than 100% as measured by clock speed, device area, and power consumption) and productivity gains (should be at least 100X as measured by development engineer-hours) compared with hand-coding for the pilot demonstration, plus new target hardware and/or domain-specific functionality. The report shall also document any scientific advances that have been achieved under the program. (A brief statement of claims supplemented by publication material will meet this requirement.) Final PI meeting presentation material. PHASE III DUAL USE APPLICATIONS: FPGAs and ASICSs are used extensively in embedded applications across both commercial and DoD/military fields. A commercial example of FPGA use is in automobiles for such applications as RADAR and LIDAR processing to support autonomous driving. Military applications include Software-defined radio (SDR) communications processing. Ontology-based EDA has the potential to make the development of such FPGA applications quicker, easier, and less expensive with shorter time-to-deploy and more flexibility to adapt to changing circumstances. REFERENCES: 1. K. Asanovic, et al. The landscape of parallel computing research: A view from Berkeley. Technical Report UCB/EECS-2006-183, EECS Department, University of California, Berkeley, 2006. 2. E. L. Kaltofen, “The ‘Seven Dwarfs’ of Symbolic Computation,” In: Langer U., Paule P. (eds) Numerical and Symbolic Scientific Computing. Texts & Monographs in Symbolic Computation (A Series of the Research Institute for Symbolic Computation, Johannes Kepler University, Linz, Austria). Springer, Vienna, 2012. KEYWORDS: EDA, ontology, SoC, heterogeneous, FPGA, Verilog, VHDL
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