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Side Channels for Heterogenous Integrated Circuits


OUSD (R&E) MODERNIZATION PRIORITY: Microelectronics TECHNOLOGY AREA(S): Electronics OBJECTIVE: Determine if functions in individual chips on a heterogenous integrated circuit can be detected through side channels. DESCRIPTION: A heterogenous integrated circuit (HIC) consists of multiple different integrated circuits (ICs), such as central processing units (CPUs), graphic processing units (GPUs), field programmable gate arrays (FPGAs), and on-chip accelerators (neural network accelerators) on a single, larger integrated package. To date, side channels have looked for vulnerabilities and emissions in single purpose ICs only (e.g. CPUs and GPUs). New state-of-the-art packaging techniques already have integrated multiple different types of ICs onto a single package. Identifying the contributions of the individual ICs to the overall composite signal of the side channel is an important first step to defining potential mitigations. This SBIR topic seeks to explore multiple different potential approaches to differentiate individual ICs and their functions from the composite side channel signal measured on the HIC. In order to quantify the different approaches and their feasibility, the expected performance metrics for Phase I and Phase II are described in Table 1. Proposers should be able to provide comparison to the current state of the art (with references) and clearly describe how their approach is intended meet or exceed the metrics. Phase Probability of Detection Probability of False Alarm # of integrated circuits End of Phase 1 80% 0.01% 2 End of Phase 2 90% 0.01% 4 PHASE I: The goal of Phase I is to identify signal components that contribute to the composite side channel from a HIC containing two or more heterogenous ICs. The proposer should be able to articulate what composite side channel(s) are being used and why those side channel(s) were selected. The selected side channels shall be extensible, that is, they should be able to model and predict behaviors on other types of ICs. When identifying the components, the performer shall have a probability of detection of at least 80% and a probability of false alarm of less than 0.01% by the end of Phase I. Schedule/Milestones/Deliverables • Month 1: Report and presentation on initial algorithms • Month 2: Report on experimental set up • Month 3: Report on acquisition of different integrated circuits and initial conditions • Month 4: Interim report describing current experimental results • Month 5: Interim report describing current experimental results and potential extensibility • Month 6: Final Phase I Report summarizing approach; results; comparison with alternative state-of-the-art methodology; quantification of probability of detection; quantification of probability of false alarm; and quantification of extensibility Proposers interested in submitting a Direct to Phase II (DP2) proposal must provide documentation to substantiate that the scientific and technical merit and feasibility described above has been met and describes the potential military and/or commercial applications. Documentation should include all relevant information including, but not limited to: technical reports, test data, prototype designs/models, and performance goals/results. PHASE II: Phase II efforts should refine the extensibility of the algorithms developed in Phase I for additional ICs. Potential additional side channels should be analyzed if the methodology from Phase I is not sufficiently extensible. At the end of Phase II, at least four or more unique ICs (not copies of the same integrated circuit) in a single HIC should be separable from the overall composite side channel. Schedule/Milestones/Deliverables • Month 2: Report on lessons learned, updated algorithms, and potential additional ICs to be evaluated • Month 4: PI meeting, including demonstration of progress to date, PowerPoint presentations of accomplishments and plans • Month 6: Interim report quantifying the effects of real-world noise and other potential contributions that could cause issues with separation of the signals • Month 9: Interim report describing the theory behind the specific side channel(s) used and interim demonstration of capabilities • Month 12: Interim report on progress to date • Month 15: Interim report on progress to date and final demonstration plans • Month 16/17: Final demonstration of developed tools and capabilities • Month 18: Final Phase II Report summarizing approach, results, comparison with alternative state-of-the-art methodology, quantification of probability of detection, quantification of probability of false alarm, theory of side channel contributions, and quantification of extensibility (ability to model and predict behaviors on other ICs) PHASE III DUAL USE APPLICATIONS: Heterogenous integrated circuits are starting to become a larger and larger part of both commercial and DoD/military systems. Identifying how side channels are convoluted when measuring multiple ICs supports the eventual exploration of mitigation paths to these. Mitigating side channels in HICs enables increased signal quality within the package and reduction of potential information leakage of a heterogenous integrated circuit. REFERENCES: 1. “Apple unveils M1 Ultra, the world’s most powerful chip for a personal computer.” [Online], Available: [Accessed: July 8, 2022] 2. T. Kasper, D. Oswald, and C. Paar. "Side-channel analysis of cryptographic RFIDs with analog demodulation." International workshop on radio frequency identification: Security and privacy issues. Springer, Berlin, Heidelberg, 2011. 3. P. Kocher, J. Jaffe, and B. Jun. "Differential power analysis." Annual international cryptology conference. Springer, Berlin, Heidelberg, 1999. 4. J. Ferrigno, and M. Hlaváč. "When AES blinks: introducing optical side channel." IET Information Security, vol. 2, issue 3, pp. 94-98, 2008 KEYWORDS: Microelectronics, Side Channels, Hardware Security, Heterogenous Integrated Circuits, System on Chip, Cyber Security
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