Description:
OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Microelectronics; Quantum Science
OBJECTIVE: An application-specific electronics package that enables low-noise miniaturization of quantum systems.
DESCRIPTION: Quantum systems rely on electronics for control and signal input/output to larger systems. Often, these originate with large scale lab electronics, then are scaled down to field programmable gate arrays (FPGA) to enable modularity. However, FPGAs can be large, expensive, power hungry, and potentially introduce unknown and undesired threats. Application-specific electronics can be one approach to overcoming the limitations of an FPGA. Application specific electronics can include, but are not limited to, custom printed circuit board design or application-specific integrated circuit (ASIC) development. An ASIC is the smallest SWaP and typically lowest noise solution but has a high barrier to entry as it includes high non-recurring engineering costs and long wait times, due to the business model of IC foundries. This SBIR topic aims to lower the investment required by small businesses to creating custom, specific electronics and packaging for quantum sensors, in order to increase TRL and the ability to bring small quantum sensors to market.
PHASE I: Use of IC foundries can be arduous and include long lead times. Phase I of the topic should include design of the application specific electronics, identifying and negotiating with a trusted IC foundry for fabrication, and receiving the process design kit (PDK) from the foundry of choice. The outcome of Phase I should be that the performer is ready to move forward to procure an ASIC with a foundry, either with dedicated wafers or as part of a multi-project wafer (MPW) run.
Alternatively, Phase 1 can be to develop application specific, custom electronics on a printed circuit board. The product of Phase I is a detailed report outlining the design, including modeling and simulation, and a detailed plan for fabrication. One key component for this critical technology, will be to consider the ‘trust’ of the vendor. The Phase I deliverable should outline the risk management and quality assurance of safeguarding against any IP threats. Phase I Base amount must not exceed $290,000 for a 12-month period of performance.
PHASE II: The Phase II goal of the SBIR is to integrate and demonstrate the custom electronics packaged with and operating with the quantum sensor of choice. The Phase II deliverable is a report outlining the electronics design and fabrication, as well as integration tests and demonstration results. Ideally, the custom electronics integrated with a quantum sensor will become a government off-the-shelf component for procurement. The custom, packaged electronics should dramatically reduce cost, size, weight and power necessary for operating quantum sensors, thereby creating a viable transition path to the warfighter. Phase II Base amount must not exceed $1,000,000 for a 24-month period of performance and the Option amount must not exceed $900,000 for a 12-month period of performance.
PHASE III DUAL USE APPLICATIONS: One military application would be to create the custom electronics necessary for a quantum-based clock, such as a photonic integrated chip that requires IC fabrication for photonics and electronics. The product to be included with the quantum clock, would require packaging. Alternatively, there are chip-scale quantum sensors, such as SQUID arrays that require custom electronics packaging and electronic interfaces. This SBIR topic covers the electronics design, fabrication, and packaging for this class of EM sensor.
REFERENCES: Charbon, E. Cryo-CMOS Electronics For Quantum Computing: Bringing Classical Electronics Closer To Qubits In Space And Temperature. IEEE Solid-State Circuits Magazine 13, 54–68 (2021).
KEYWORDS: Quantum; atomic; asic; low-swap; quantum sensor; packaging
