Description:
OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Microelectronics
OBJECTIVE: This topic seeks to develop a super-resolution thermal metrology tool to enable accurate characterization of semiconductor materials and devices, and wide bandgap and ultra-wide bandgap materials and devices, in particular, at nanometer length scale.
DESCRIPTION: Radar and communication systems are ubiquitous in both military and commercial applications. In these platforms, system performance can be improved by increasing the radio frequency (RF) output power of the transmitter power amplifier (PA), which is directly proportional to the output power density of the PA transistor. However, the operating output power densities achieved in today’s wide bandgap transistors are thermally limited to values substantially below theoretical electronic limits. The government has an interest in developing technologies to overcome these thermal limitations and realize robust, high-power density transistors that operate near their fundamental electronic limit of RF output power, with a focus on achieving high power density through reduction in transistor thermal resistance [1]. Success requires metrology that can accurately measure thermal resistance and interfacial thermal resistance of a variety of material and device structures. Furthermore, these measurements are required to verify that performer high-power transistors meet program metrics.
Existing thermal metrology tools often use pump-probe laser-based techniques, such as time-domain thermoreflectance (TDTR), frequency-domain thermoreflectance (FDTR), and recent variants such as steady state thermoreflectance (SSTR)[2] . While these techniques are useful for the measurement of thermal resistance in thin films and interfaces, they are are limited in spatial resolution [2,3], and cannot measure thermal resistance and thermal resistance gradients in submicron devices. The ability to measure thermal resistance beyond the surface film (i.e., in the buried channel layer of a heterojunction device) and also characterize at both nanoscale and microscale dimensions, is critical to the development of high power density devices. The purpose of this direct to Phase II (DP2) SBIR topic is to develop a super-resolution thermal metrology tool that enables accurate characterization of the thermal resistance of semiconductor materials, heterostructures and devices, particularly wide bandgap and ultra-wide bandgap materials and devices at nanometer length scale. The tool must be capable of measuring both epilayers and operating devices with a thermal resolution less than 0.25 oC, thermal precision of 1 oC, spatial resolution below 50 nm, accuracy above 90%, and reproducibility and repeatability less than 2%. Specific measurement capabilities include thermal resistance, thermal boundary resistance of interfaces, and temperature of an operating device and, in particular, buried channel layers. The device-scale measurements must characterize both the surface and cross-section of a multi-finger, submicron GaN high-electron-mobility transistor (HEMT) and an ultra-wide bandgap AlGaN HEMT. In addition, a comprehensive validation plan should be provided. For example, the plan should include device-relevant material structures, such as GaN transistor layers, that are compared to other thermal measurement techniques for verification of results. The plan may also incorporate National Institute of Standards and Technology (NIST) standards. The final Phase II base deliverable will be a laboratory demonstration of the thermal metrology tool, along with a plan for construction of tool and delivery to a U.S. government organization. The Phase II option of this topic will address the development of this thermal metrology tool into an automated, turnkey system that will be delivered to a U.S. government laboratory. The deliverables of the Phase II option will include both the tool, calibration standards, and any necessary software for demonstrating material and device thermal characterization. Finally, on-site support will be required to ensure proper installation and operation at the U.S. government organization.
PHASE I: This topic is soliciting Direct to Phase II (DP2) proposals only. This DP2 SBIR requires documentation of existing thermal metrology capabilities and a proposed plan with supporting analysis showing that achieving 50 nm spatial resolution with high precision and accuracy is feasible. The documentation must include measured data, including thermal resistance, from existing thermal metrology techniques demonstrating less than 2 µm spatial resolution and the ability to resolve interfaces beyond the surface film. In addition, validation data from the existing thermal metrology tool should be provided.
PHASE II: The proposed plan must describe the path towards a successful final DP2 SBIR deliverable which meets the requirements listed below. This DP2 SBIR will have an 18-month duration in which the super-resolution thermal metrology tool will be designed, developed, validated, and tested for performance goals. The requirements of the thermal metrology tool are:
1. Capable of measuring thermal resistance, thermal boundary resistance, and temperature of operating multi-finger, submicron GaN HEMT and ultra-wide bandgap AlGaN HEMT with the following specifications:
a. Spatial resolution < 50 nm
b. Thermal resolution < 0.25 oC
c. Thermal precision: 1 oC
d. Accuracy > 90%
e. Reproducibility and repeatability < 2%
2. Tool validation using a comparison of measured results of device relevant structures to other thermal metrology techniques. In addition, validation may use available NIST standards.
Phase II (base) fixed milestones include:
• Month 1: Detailed report on super-resolution thermal metrology tool design, including documentation of path towards achieving in-situ device testing and meeting DP2 SBIR goals.
• Month 3: Report on progress towards final design and demonstration of thermal metrology tool.
• Month 6: Report on progress towards final design and demonstration of thermal metrology tool.
• Month 9: Report on progress towards final design and demonstration of thermal metrology tool.
• Month 12: Initial prototype demonstration of super-resolution thermal metrology tool. Detailed report should include validation data as well as thermal resistance, temperature, and thermal resolution of the surface and cross-section of GaN and AlGaN transistors with less than 100 nm spatial resolution. Documentation should also describe the path towards the final DF2 SBIR deliverable.
• Month 15: Detailed report on progress towards final design and demonstration of the thermal metrology tool, including validation data and transistor thermal characterization.
• Month 18: Final demonstration of a prototype thermal metrology tool that meets requirements listed above. Detailed data report containing final validation measurements and thermal characterization of surface and cross-section of GaN and AlGaN transistors with less than 50 nm spatial resolution. Plan for construction of tool and delivery to a U.S. government organization.
Phase II (option) This DP2 SBIR will have a 6-month option in which the super-resolution thermal metrology tool demonstrated in Phase II will be developed into a turn-key, push-button, automated system. A Phase II option final report will detail the successful demonstration of a fully-automated measurement of the thermal resistance, thermal boundary resistance, temperature, and thermal resolution of an operating multi-finger, submicron GaN HEMT and ultra-wide bandgap AlGaN HEMT. The DP2 option will also include:
1. Delivery of prototype automated, turnkey thermal metrology tool to a designated U.S. government organization.
2. Support for installation and operation at the U.S. government laboratory.
3. Demonstration of thermal characterization of GaN HEMT and ultra-wide bandgap AlGaN HEMT on-site at the U.S. government organization.
Phase II (option) fixed milestones include:
• Month 1: Detailed report on automated, push-button thermal metrology tool design and path toward achieving DP2 Option goals. Coordinate with the designated U.S. government organization to provide a preliminary plan for delivery and installation.
• Month 3: Report on thermal metrology tool development progress.
• Month 6: Delivery of final prototype thermal metrology tool, including calibration standards and any necessary software for demonstrating material and device thermal characterization. Detailed report containing final validation measurements and thermal characterization of surface and cross-section of GaN and AlGaN transistors with less than 50 nm spatial resolution.
PHASE III DUAL USE APPLICATIONS: This SBIR will enable a commercially available, automated thermal metrology tool for use by academia, semiconductor foundries (commercial and defense), and material vendors. Specifically, this technology will provide high resolution thermal metrology so that transistor developers can accurately characterize the thermal resistance and temperature of a wide variety of films, material structures, devices, and packages. This thermal characterization data can be incorporated into device modeling and design, enabling devices with higher power density and improved robustness for a wide range of defense and commercial radar and communication applications.
REFERENCES:
[1] DARPA Broad Agency Announcement, Technologies for Heat Removal in Electronics at the Device Scale (THREADS), Microsystems Technology Office, HR001123S0013, November 18, 2022.
[2] Olson, David, et al., "Spatially resolved thermoreflectance techniques for thermal conductivity measurements from the nanoscale to the mesoscale", Journal of Applied Physics 126, 2019.
[3] Yuan, Chao, et al., “A review of thermoreflectance techniques for characterizing wide bandgap semiconductors’ thermal properties and devices’ temperatures,” Journal of Applied Physics 132, 2022.
KEYWORDS: Microelectronics, thermal metrology, thermoreflectance, thermal resistance, temperature, transistor, wide bandgap, ultra-wide bandgap
