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Low Cost, High Performance SiC Junction Barrier Schottky Diodes for Grid Applications

Award Information
Agency: Department of Energy
Branch: N/A
Contract: DE-SC0024128
Agency Tracking Number: 0000274632
Amount: $206,500.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: C56-08a
Solicitation Number: DE-FOA-0002903
Timeline
Solicitation Year: 2023
Award Year: 2023
Award Start Date (Proposal Award Date): 2023-07-10
Award End Date (Contract End Date): 2024-04-09
Small Business Information
20 Harold Ave D1
Santa Clara, CA 95050
United States
DUNS: N/A
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Jin Seo
 (408) 761-0598
 jinho.seo@thinsic.com
Business Contact
 Matthew Coda
Phone: (415) 734-6226
Email: matt@aegiscreek.com
Research Institution
N/A
Abstract

ThinSiC proposes to demonstrate the feasibility of making ultra-thin silicon carbide (SiC) Junction Barrier Schottky Diodes (JBSD) with vastly improved thermal conduction, lower defect density, lower cost of production, and eliminating the need to waste SiC substrates, as done in standard manufacturing methods. Here, ThinSiC will also identify failure modes and unanticipated hurdles in production prior to scalability. Our approach combines lateral SiC epitaxy and our proprietary separation method. ThinSiC has already demonstrated in the lab separation of thin single crystal epitaxial SiC layers from the SiC substrate. Thus, understanding and quantifying the impact of these methods on device performance will retire a significant risk to productization. Since SiC JSBDs can be drop-in replacements for Si JSBDs while operating at higher efficiencies, this proposed Phase I project has the potential to have meaningful near-term market impact. SiC is widely viewed as a “better” material for high-power power electronics (PE) applications because of its higher bandgap, higher breakdown voltage and higher thermal conductivity. However SiC is expensive to use and traditional manufacturing approaches result in relatively thick devices that do not fully capitalize on the material properties. Today, SiC dies cost 10x more than their Si counterpart, and packaged SiCbased devices are 3X more costly than equivalent Si devices. This is due entirely to the dramatically higher SiC substrate cost. Furthermore, n production, 70% of the SiC substrate is wasted by grinding - a required step in conventional manufacturing approaches to achieve a thinner substrate for reduced RDSon. This significantly drives up costs of using SiC substrates in JSBD. ThinSiC’s technology addresses this problem by completely eliminating the grinding step in vertical power device fabrication. Not only does ThinSiC’s approach allow reuse of individual wafers, it allows for the manufacture of very thin devices without subjecting the dies to the mechanical stress of grinding. Lowering the costs of SiC for JSBD, and eventually other SiC devices, will expand the utilization of SiC in commercial products by improving their utility, affordability, and accessibility. Replacement of Si power electronics devices with SiC devices is a readily achievable route to higher efficiency and higher performance power electronics for high power applications (grid switches, power conditioners, inverters, etc.), if the production costs can be lowered by 30-50%. If successful, ThinSiC will proceed toward Phase II to further optimize our approach preparation for scalability by expanding the process on a 6-in SiC wafer and ensuring the separation of the ultra-thin layer from the substrate can be performed without damaging the epilayer. ThinSiC will perform long-term stability testing and pursue pilot testing with an industry partner.

* Information listed above is at the time of submission. *

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