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High Performance (CMOS) Imagers with Robust On-Chip Processing

Award Information
Agency: Department of Defense
Branch: Army
Contract: N/A
Agency Tracking Number: 36904
Amount: $97,348.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Solicitation Year: N/A
Award Year: 1997
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
5055 Corporate Plaza Dr, Suite 100
Colorado Springs, CO 80919
United States
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 David W. Gardner
 (719) 599-7700
Business Contact
Phone: () -
Research Institution

High-speed large-format solid state imaging devices have been used for several years in a variety of scientific, industrial, and consumer applications. As the format size increases, however, the problem of post-capture processing becomes significantly larger, not only in terms of raw memory required but also in terms of processor throughput. Ideally, an imager capable of performing significant processing of the image on-chip, including analog-to-digital conversion but prior to storage, would greatly reduce the processor overhead and open up new applications heretofore unimagined. The imaging device structure proposed herein will provide this on-chip processing capability, as well as several other advantages over current imaging technologies which are detailed as well. Imaging areas which would benefit include all areas in which noisy or less-than-perfect images must be acquired and post-processed in order to extract useful information. Areas which would benefit from such an "intelligent" CMOS imaging include, but are not limited to, machine vision and inspection, surveillance; remote sensing, digital photography, X-ray medical imaging, and high-speed imaging in any noisy environment.

* Information listed above is at the time of submission. *

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