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DEPOSITION OR INP ON SI SUBSTRATES FOR MONOLITHIC INTEGRATION OF ADVANCED ELECTRONICS

Award Information
Agency: Department of Defense
Branch: Missile Defense Agency
Contract: N/A
Agency Tracking Number: 6474
Amount: $496,000.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Timeline
Solicitation Year: N/A
Award Year: 1988
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
Patriots Pk
Bedford, MA 01730
United States
DUNS: N/A
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Stanley M Vernon
 (617) 275-6000
Business Contact
Phone: () -
Research Institution
N/A
Abstract

A PROCESS IS BEING DEVELOPED FOR THE HETEROEPITAXIAL GROWTH OF INP ON SILICON SUBSTRATES BY METALORGANIC CHEMICAL VAPOR DEPOSITION. DUE TO ITS ELECTRON SATURATED DRIFT VELOCITY AND RADIATION RESISTANCE, INP ISAN EXCELLENT MATERIAL FOR USE IN HIGH SPEED ELECTRON DEVICES AND SPACEAPPLICATIONS. SILICON IS AN OPTIMAL SUBSTRATE MATERIAL DUE TO THE AVAILABILITY OF HIGH PURITY, LARGE AREA, LOW COST WAFERS. COMPARED TOINP, SI HAS VERY HIGH STRENGTH-TO-WEIGHT RATIO AND THERMAL CONDUCTIVITY. THE GROWTH PROCESS BEING DEVELOPED WOULD PROVIDE HIGH QUALITY, SINGLE CRYSTAL INP ON SI THAT COULD LEAD TO THE ESTABLISHMENTOF AN INP-ON-SI DEVICE TECHNOLOGY. IN THE INITIAL RESEARCH EFFORT, THE FEASBILITY IS BEING DEMONSTRATED OF DEPOSITING SINGLE-CRYSTAL FILMS OF INP ONTO SI SUBSTRATES AND THE STRUCTURAL PROPERTIES OF THESEFILMS CHARACTERIZED. OPTIMIZATION OF THE GROWTH PARAMETERS AND DEMONSTRATION OF DEVICE-QUALITY MATERIAL WOULD BE SUBJECTS OF A LATER RESEARCH EFFORT. THE DEVELOPMENT OF A GROWTH PROCESS FOR INP ON SILICON WOULD PROVIDE A STRONG BASIS FOR THE DEVELOPMENT OF LARGE SCALE INTEGRATION OF HIGH SPEED, RADIATION HARD INP DEVICES ON HIGH QUALITY, LOW COST, LARGE AREA SUBSTRATES. THE DEVELOPMENT OF DEVICE QUALITY INP ON SILICON COULD BE EFFECTIVELY UTILIZED IN TRANSISTORS, PHOTODETECTORS, LASERS, MICROWAVE COMMUNICATIONS DEVICES, AND THE MONOLITHIC INTEGRATION OF INP OPTOELECTRONIC DEVICES WITH SILICON LOGIC CIRCUITS.

* Information listed above is at the time of submission. *

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