Description:
OBJECTIVE: Develop homoepitaxial GaN high voltage (5000V) vertical power switching transistors on GaN substrates to enable compact, efficient high power converters. DESCRIPTION: GaN power switching transistors have recently been demonstrated with performance superior to conventional silicon (Si) or silicon carbide (SiC) based devices. The demonstrated GaN devices offer a better combination of on-resistance, capacitance and breakdown voltage than competing technologies. However, GaN devices have been limited by the non-native substrates (such as Si or SiC) required to date. The heteroepitaxy of GaN material on non-GaN substrates has led to lower quality material and required thick GaN buffer layers to support the depletion region required for high voltage devices, limiting practical devices to ~1,500 volts (V). The recent and on-going development of high quality bulk GaN substrates offers the new possibility of GaN transistors developed homoepitaxially on GaN substrates. This approach would reduce the requirement for thick GaN buffers, lowering materials growth and process costs, as well as, open the door to new power device topologies, such as vertical devices, which could potentially support up to 5 kilovolts (kV) with 50% lower resistance versus SiC devices. State of the art is focused on Si, SiC and GaN devices. Si devices are the most mature but disadvantaged relative to Wide Bandgap (WBG) materials (SiC and GaN) due to fundamental materials aspects that limit breakdown field and on-resistance. SiC materials are similar to GaN but are more developed with demonstrated Depletion Metal Oxide Semiconductor Field Effect Transistor (DMOSFET) devices operating up to 15kV. Due to higher critical breakdown field, GaN offers the best combination of fundamental materials properties for power switching but has been exclusively developed on non-GaN substrates to date. GaN Schottky diodes have been demonstrated to benefit from free standing substrates, but this effort will focus on transistor structures. PHASE I: Design/develop an innovative concept that demonstrates the scientific merit and feasibility of developing a normally-off, high voltage Field Effect Transistor (FET) technology in GaN on native GaN substrates. The effort will demonstrate a device approach that provides a blocking voltage of 5,000V, a threshold voltage>1V, with a specific on-resistance, RDS,ON-SP of 30 mOhm-cm2. These specifications are to be achieved in a vertical device geometry that is capable of comparable frequency response characteristics to current SiC power switching devices. PHASE II: Demonstrate a device with a 1 amp drain current while maintaining the blocking voltage at 5,000V, a threshold voltage>2V, and reducing the on-resistance, RDS,ON-SP to 20 mOhm -cm2. In addition the drain current collapse, RAC/RDC, at 600V, will be<3. Device yield on-wafer should be>50%. PHASE III: Demonstrate a device with a 5 amp drain current with a blocking voltage to 5000V, a threshold voltage>2V, and reducing the on-resistance, RDS,ON-SP to 10 mOhm-cm2. Reduce the drain current collapse, RAC/RDC, at 600V, to<1.5. Advance on-wafer yield to>90%. PRIVATE SECTOR COMMERCIAL POTENTIAL/DUAL-USE APPLICATIONS: Normally-off GaN devices will replace Si in most power applications where improved efficiency is required. This is currently a major drive in the commercial sector in an effort to reduce energy costs.
