OBJECTIVE: To research and develop an innovative, programmable, low-power, neuromorphic parallel processor that functions with power comparable to that of the biological neuron that is 1000 times more power efficient than popular processors available today. DESCRIPTION: The US Army ARDEC is in search of a novel means to address the urgent need for a low-power parallel processor with functionality similar to that of the biological neuron to facilitate massive computational resources necessary to support un-manned aerial systems (UAS) applications, such as digital imaging, acoustic processing, and other power intensive applications. This technology can reduce the cost of precision munitions by providing in-flight and terminal guidance. Standard systems have demonstrated that their ability to process and integrate data from various modalities is insufficient to provide valuable information judiciously. In addition, power constraints are often a restrictive factor when considering deployment in theater. Due to the limitations of conventional processor technologies, there is a critical necessity for a fundamentally unique processor in which the goal is to supply adequate computational capability with optimal and acceptable power requirements. The goal of this effort will be to design a parallel processor based on the neuromorphic characteristics of the biological neuron. Leveraging the efficiency of the human brain, based on numerous electro-chemical mechanisms and neuronal activity, provides an innovative methodology for logic interpretation and the transmission of signals. Considerable investigation has gone into the modeling and simulation of the human brain and its neuronal components. This has led to the development of hardware configurations that can emulate neuronal behavior and functionality called neuromorphic architectures. Understanding the various components in these architectures has allowed for the development of complex simulations in software as well as small-scale, prototype integrated circuits. A predominant amount of this work has been performed to comprehend neuronal operation rather than prioritizing the application of neuromorphic concepts for a utilizable processor with favorable size, weight and power attributes. To accurately emulate the cellular neuron and all its intricacies it will be necessary to incorporate a mixed-mode element to accurately implement the integration of signals as in the neurons within the brain. These elements should consist of several individual neurons with the ability for their interconnections to be reconfigured dynamically. To augment processing capabilities and decrease power necessity, the internal network should be able to execute in parallel with the potential for the sub-units to be interconnected and networked for dedicated applications, as in the brain. PHASE I: In Phase I, the contractor shall create one or more innovative and practical designs that leverages various neuromorphic research and development efforts to develop a technical approach for a low-power neuromorphic parallel processor. The technical approach should include the various bio-inspired components included within the proposed neuromorphic design as well as how these elements will implemented in a prototype solution. The proposed approach must demonstrate the ability for numerous neurons to operate simultaneously in parallel or/and in series with a timely data flow between the neurons and outside stimuli. In addition, details should be provided on the dual analog/digital capabilities of the neuron as well as the ability to reprogram interconnections (synapses) dynamically. Phase I should present a fundamental advancement in processor technology and provide a framework for which consequent phases can be supported. Deliverable of Phase I should be a paper study demonstrating feasibility of concept. PHASE II: Phase II will consist of a complete prototype neuromorphic architecture design, simulation to ensure communication and system design functions properly, and a manufactured hardware chip with the appropriate semiconductor technology based upon the selected architecture. The neuromorphic design should be equivalent to the processing power of fifty million neurons in a package that weighs less than thirty grams, occupies less than fifteen cubic centimeters, and operates on less than two pico-Joules per operation. Current state-of-the-art neuromorphic processors utilize slightly under 1 watt per 1 million neurons on a compact, portable device. IBMs BlueGene project simulates in software 1.6 billion neurons and 8.87 trillion synapses with the C2 cortical supercomputer. The neuromorphic processor must be fully programmable through self or guided learning. The memory, i.e., synaptic junctions, should be greater than one hundred per neuron. The devise should be interfaced to a laptop for programming, control, and graphical user interface. Prior to fabrication, the full up prototype design shall be thoroughly evaluated through computer simulation of all components and their integrated whole to provide the highest level of confidence that the prototype will function as a neuromorphic system. The simulations shall include execution of multiple types of mathematical and logic algorithms, self learning, that is, self adjustment of synaptic strengths based on changes in outside stimuli, and power off with full recovery to the learned state prior to power off. Multiple simulations should be executed in which the processor correctly identifies hundreds of graphical structures where the outside stimuli is equivalent to that which would come from ten thousand rods in the human eye viewing those structures. Deliverable of Phase II should be a prototype of the neuromorphic system. PHASE III: This technology will support many applications where computational requirements are severe while power consumption must be at the lowest possible level. Applicable mission related activities include surveillance, reconnaissance (ISR), automated target recognition and detection, IED detection, and acoustic processing. Commercial applications include any intensive processing applications such as imaging devices (hyperspectral imaging). REFERENCES: 1. J G Elias, H H Chu and S Meshreki, A neuromorphic impulsive circuit for processing dynamic signals, IEEE International Conference on Circuits and Systems, pp 2208-2211, IEEE Press, 1992. 2. M Simoni, G Cymbalyuk, M Sorensen, R Calabrese. and S DeWeerth, A multi-conductance silicon neuron with biologically matched dynamics, IEEE Trans. Biomed. Eng, pp 342-354.IEEE Press, 2004 3. A Chandrasekaran and K Boahen, A 1-change-in-4 Delay-Insensitive Interchip Link, IEEE International Symposium on Circuits and Systems, IEEE Press, 2010. 4. J V Arthur and K Boahen, Silicon Neurons that Inhibit to Synchronize, IEEE International Symposium on Circuits and Systems, pp 4807-10, IEEE Press, 2006. 5. K M Hynna and K Boahen, Neuronal Ion-Channel Dynamics in Silicon, IEEE International Symposium on Circuits and Systems, pp 3614-17, IEEE Press, 2006. 6. J Lin, P Merolla, J Arthur and K Boahen, Programmable Connections in Neuromorphic Grids, 49th IEEE Midwest Symposium on Circuits and Symtems, pp 80-84, IEEE Press, 2006.