You are here

Characterization and Mitigation of Radiation Effects in Nonplanar Nano-technology Microelectronics

Award Information
Agency: Department of Defense
Branch: Defense Threat Reduction Agency
Contract: HDTRA1-12-C-0003
Agency Tracking Number: T2-0184
Amount: $747,727.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: DTRA092-001
Solicitation Number: 2009.2
Solicitation Year: 2009
Award Year: 2011
Award Start Date (Proposal Award Date): 2011-11-15
Award End Date (Contract End Date): N/A
Small Business Information
215 Wynn Dr., 5th Floor
Huntsville, AL -
United States
DUNS: 185169620
HUBZone Owned: No
Woman Owned: Yes
Socially and Economically Disadvantaged: No
Principal Investigator
 Marek Turowski
 Director of Nano Electron
 (256) 726-4800
Business Contact
 Deb Phipps
Title: Senior Contract Specialis
Phone: (256) 726-4884
Research Institution

Future high-performance integrated circuits in DoD satellite systems will require silicon-on-insulator (SOI) and non-planar nano-technology devices, such as MultiGate Field Effect Transistors (MuGFETs) or FinFETs, which can decrease pattern area of logic circuits below 50% of the conventional planar technologies. However, the single-event-effect (SEE) response of non-planar devices and circuits is unknown. To enable characterization and mitigation of SEEs in such technologies, CFDRC, in collaboration with Vanderbilt University (VU) and SEMATECH, is developing the following innovations: (a) First ever characterization, by modeling and experiments, of SEEs in nano-scale SOI and non-planar devices and circuits, including floating body effects and isolation-volumes related charge collection mechanisms; (b) New semiconductor physics models for the nano-technologies: microscopic charge generation in insulators, electron/hole transport in various insulators and insulator-silicon interfaces, implemented in CFDRC"s NanoTCAD 3D/mixed-mode simulator; and (c) Simulation-supported design and validation of mitigation techniques for SEEs. In Phase I, representative advanced FinFET and SOI devices and circuits were successfully used for"proof-of-concept"modeling, validated with experimental data, and characterized for SEEs by means of 3D/mixed-mode simulations. In Phase II, we will perform computational and experimental studies to quantify the floating body and isolation volume related mechanisms, and implement improved models in the NanoTCAD simulator. SEE mitigation methods will be explored, verified, and demonstrated.

* Information listed above is at the time of submission. *

US Flag An Official Website of the United States Government