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Radiation Hardened Low Power Variable Bandwidth/Resolution Sigma Delta Converters


OBJECTIVE: Identify concepts and architectures for radiation hardened sigma delta ADCs (analog to digital converters) and DACs (digital to analog converters) for application in satellite control systems. DESCRIPTION: Satellite systems rely on numerous servo systems to control antennas, thrusters, gyros, and many other mechanical functions. Critical elements in many of these systems are high resolution ADCs and DACs. Typically, these applications require relatively low bandwidth (<10 MHz) but need high resolution (16 to 22 bits) with high signal to noise ratio (114 db). In many cases, there are opportunities for trading off resolution and bandwidth with higher precision available for lower bandwidth and vice versa. As with all space electronics, there is significant benefit in reducing the size, weight, and power in the ADC and DAC. Proposals are requested for sigma delta architectures for either ADCs or DACs that are optimized for space applications. The proposals shall indicate the provisions that have been incorporated to address the unique requirements of space applications and the environmental challenges of multi-year space missions. General requirements for the rad hard, low power, variable bandwidth ADC or DAC: The ADC or DAC proposal shall address the following: (a) the development of a design architecture capable of variable bandwidth/resolution while maintaining low power operation in a space environment; (b) the design and fabrication of either an ADC or DAC with the targeted characteristics; (c) provisions for radiation hardening to the space environment (total dose hardness>300 krad(Si), no single event latch-up, no single event functional interrupts, and error management for single event upset from heavy ions or protons). PHASE I: The contractor shall develop an architecture for an ADC or DAC consistent with the requirements above. The effectiveness of the proposed architecture shall be demonstrated via simulation. The approach to design, fabricate, and test a radiation hardened version shall be clearly stated. PHASE II: The contractor shall design, fabricate and test either an ADC or DAC based on the architecture developed in the phase 1 activity. Testing shall include electrical verification of performance and demonstration of the radiation hardness. PHASE III: This research supports a broad range of military space, ground and aviation applications which utilize digital signal processing. A robust amount of commercial applications will result in above areas. REFERENCES: 1. Sansen, W., Katholieke Univ., Leuven,"Mixed analog-digital design challenges"Systems on a Chip (Ref. No. 1998/439), IEE Colloquium on, 5 Sep 1998. 2. Edwards, C.F.; Redman-White, W.; Bracey, M.; Tenbroek, B.M.; Lee, M.S.L.; Uren, M.J."A multibit S modulator in floating-body SOS/SOI CMOS for extreme radiation environments", Solid-State Circuits, IEEE Journal of, 1999, 34(7):937-948. 3. M. Ortmanns and F. Gerfers, Continuous-time sigma-delta A/D conversion: fundamentals, performance limits and robust implementations. Springer Verlag, 2006. 4. A. Agah, K. Vleugels, P. B. Griffin, M. Ronaghi, J. D. Plummer, and B. A. Wooley,"A high-resolution low power incremental sigma-delta ADC with extended range for biosensor arrays,"IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 10991110, 2010.
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