You are here

High Density Optical Interconnects

Description:

OBJECTIVE: Demonstrate low-loss, high density optical waveguides suitable for chip-scale integration with layout and pitch comparable to next generation global-level interconnects. Identify and demonstrate active components beyond the state-of-the-art by incorporating these waveguides. DESCRIPTION: The use of optics has revolutionized communications due to its extremely large bandwidth, very low propagation loss and its intrinsic lack of electromagnetic interference. Historically, optical signaling began to uproot wired electronic communications with long trunk telecommunications lines. As the technology and manufacturing processes improved and reduced costs, the minimum link for which optics was superior became shorter every year. Today it is clear that high data-rate optical links can outperform their wired counterparts for links greater than a few centimeters. It is the short range electrical interconnect, however, that is principal source of energy dissipation in modern computing systems. In integrated circuits, performance and power efficiency improve with reducing the size of the system through scaling. For instance, the capacitance per unit length of an interconnect element tends to remain constant through geometric scaling. Because the loss of the line will scale as capacitance, the size reduction of the components and interconnects will reduce the total length and therefore the total power consumption. This reduction in communication costs was one of the original motivations for circuit integration. Miniaturization, however, cannot continue indefinitely. Although physical limitations such as ohmic resistance due to grain boundary scattering will increase with scaling, the principal limitation is due to the total number of lines enabled by continued scaling. To give a simple picture, if we are able to double the number of transistors on a chip without increasing its size, we have approximately doubled the thermal dissipation due to interconnects. Although electrostatic signaling is efficient for low-bandwidth and short distance communications, the loss in interconnects will be a key limiter in future computing systems. The huge information carrying capacity of optical fiber networks is a result of the high frequency of an optical electromagnetic wave. Optical interconnects can have low loss and large bandwidth, however optical interconnect dimensions are typically orders of magnitude larger than electrical lines, in general limited by diffraction effects to sizes on the order of the wavelength of light (~(mu)m). Therefore, they have been unsuitable to integrate with electronic devices at the chip level and consume waveguide pitches much larger than metal wires. That said, recent research in nanophotonics has identified techniques to confine optical fields to deeply sub-wavelength scales.[1-4] This project seeks the demonstration of optical waveguides with low-loss and high density as required for future interconnects. In addition to mitigating loss for high density interconnects, successful demonstration of highly confined fields will also provide several ancillary benefits for active devices. The limiting parameters of optical modulators, such as their bandwidth and driving voltage, can be significantly improved if implemented with highly confined optical fields. Other active devices, such as optical switches, can likewise be optimized. Successful development of optical interconnects will result in advanced electronic components for DoD systems with higher data throughput at lower power dissipation levels. These components will advance embedded computing applications at various sensor platforms requiring very data-intensive computations with severe power efficiency requirements. Some of the immediate benefits to the warfighter are real-time processing of complex sensor data for faster reaction times and the development of integrated, high-density optical switches and routers for extreme I/O applications. PHASE I: Through simulation and analysis, determine the technical feasibility of low-loss nano-photonic waveguides with dimensions compatible with future global interconnects. Develop a conceptual design and model key waveguide elements to provide the required confinement for on-chip integration with less than 10 dB/cm propagation loss. Define the materials, processes and fabrication steps needed to assess manufacturability and compatibility with standard integrated circuits fabrication processes. Design a preliminary concept for a high-speed, low-Vpi modulator. PHASE II: Design, fabricate, and experimentally characterize prototype, ultra-confined plasmonic waveguide devices to demonstrate dimension compatibility with electronic devices and with propagation losses below 20dB/cm. The chip-level integration requirement will be satisfied by waveguide pitch of less than 200 nm. Provide a path to achieving propagation losses below 10 dB/cm and a waveguide pitch below 100 nm. Required Phase II deliverables will include demonstration of the operation of a prototype device(s) meeting or exceeding the above specifications. In addition to waveguides, demonstrate a path to building optical couplers, modulators, switches, and multiplexers with sizes comparable to their electronic counterparts. PHASE III: For the Department of Defense, examples include specialized real time image and video processing from wide field-of-view, full-motion-video persistent surveillance systems. In general, embedded computing applications on various sensor platforms require very data-intensive computations with severe power efficiency requirements. Another key transition opportunity for the Department of Defense is in integrated, low-Vpi modulators for analog and digital photonic links. Dual Use Applications: A nanoscale photonic interconnect architecture promises to alleviate the problems associated with the interconnect bottleneck for high clock-speed computing, improving both power efficiency and performance. Applications for this technology span both the military and commercial arenas from terabit signal processors to multi-terabit per second routers. Apparent applications include data intensive computational platforms where the processing unit executes intensive I/O operations or requires considerable data transfers between different areas on the chip. Commercial Application: In the commercial space, applications range from ultra-fast on-board and off- board signal routing as well as efficient high-performance signal processors. Current high performance computing systems are moving to optical for board-to-board and box-to-box communications. In Phase III, the obvious commercial transition opportunity is in ushering optics into intra-chip communications. REFERENCES: 1. D. K. Gramotnev, S. I. Bozhevolnyi, Plasmonics beyond the diffraction limit, Nature Photonics 4, 83 (2010). 2. E. Ozbay, Plasmonics: Merging Photonics and Electronics at Nanoscale Dimensions, Science 311, 189 (2006). 3. J. Conway, S. Vedantam, H. Lee, J. Tang, E. Yablonovitch, What is the Smallest Volume Into Which Light Can Be Focused, Efficiently?, International Nano-Optoelectronics Workshop, i-NOW'07, p. 77 (2007). 4. R. Zia, J. A. Schuller, M. L. Brongersma, Plasmonics: The Next Chip-Scale Technology, Materials Today 9, 20 (2006).
US Flag An Official Website of the United States Government