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High Resolution Three-Dimensional Digital Reconstruction of Integrated Circuits

Description:

OBJECTIVE: Develop a system for the accurate identification and analysis of semiconductor materials with integrated, high-resolution imaging capability for the three-dimensional digital reconstruction of integrated circuits (ICs). DESCRIPTION: As semiconductor geometries continue to diminish, so too does the applicability of traditional sample preparation tools. As the thickness of metal layers in modern ICs drops below 100nm, existing mechanical tools become severely limited by their lack of resolution; mechanical tools are physically limited to middle sub-micron Z-axis resolution (i.e., greater than 100nm) over an entire IC area; thus, planar material removal results are unreliable at smaller technology nodes. Available non-mechanical tools (e.g., FIB), on the other hand, are prohibitively slow due to extremely gradual material removal. Ultrafast laser ablation systems have been demonstrated to have Z-axis resolution in the 100nm range, but final surface roughness can prohibit detailed analysis of the underlying circuitry. Therefore, a deep sub-micron resolution processing system with a high throughput is required for timely, accurate and precise post-silicon analysis of modern ICs. Additionally, handling and transfer of samples (between processing and imaging apparatuses) significantly contributes to the damage and contamination of delicate ICs. For this reason, in situ imaging capability is necessary to reduce these hazards and to increase the overall throughput of the system. Finally, the ability to operate in three dimensions is important because, as device architecture enters the three-dimensional frontier, the reconstruction of the de-processed IC must also become three-dimensional to properly represent the functionality of the three-dimensional architecture. PHASE I: Identify concepts and methods for failure analysis and reverse engineering using tools and techniques for the identification of semiconductor materials (e.g., Cu, Al, Si, SixOx, SixNx, W, Ti, GaAs) for the purpose of representing, in three dimensions, the constituent circuits and interconnections. Investigate existing techniques for the three-dimensional delineation of semiconductor materials within ICs. Perform a study to facilitate the design of an innovative processing/imaging system. The goal of the innovation is to process, image and digitally reconstruct (in three dimensions) the constituent features of a modern IC (e.g., interconnect traces, transistor gates, diffusion regions, vias, contacts) while adhering to the following constraints: - Z-Axis Resolution: & #8804;40nm - Image Magnification: & #8805;20,000x - Image Resolution: & #8805;50k (independent) pixels per m2 - Throughput: & #8805;0.025mm3 reconstructed per day (8 hour operator time, 24 hour tool time) @ 50nm Z resolution - Surface Roughness: & #8804;5nm RMS Deliver a report of research and innovation that presents tradeoffs between the new approach and existing technology. If any of the above constraints cannot be adhered to, the report must include relevant research and rationale. Offerors may provide alternative parameters that are both attainable and consistent with the goals summarized above. The report must also include all generated files (e.g., CAD drawings) and a program plan for system development. PHASE II: Based on the aforementioned study and applicable development/innovation, devise a novel approach and design the processing/imaging system. Determine all design decisions, understanding that implementation of the system should be in a laboratory environment with typical facility resources (e.g., nitrogen gas, DI water, 110V or 240V power @ 60Hz) and spatial restrictions. Develop a prototype of the Phase I design and demonstrate its operation. Re-verify the performance over multiple dissimilar, modern ICs (i.e., 90nm technology node or better) and develop a test plan to fully characterize the prototype. Test the prototype and deliver the prototype, characterization results, all generated files (e.g., CAD drawings, test results), operation instructions, and the test plan to the Government for further testing and verification. PHASE III: There may be opportunities for further development of this system for use in a specific military or commercial application. During a Phase III program, offerors may refine the performance of the design and produce pre-production quantities for evaluation by the Government. POTENTIAL DUAL USE APPLICATIONS: The High Resolution Three-Dimensional Digital Reconstruction system would be applicable to both commercial and government semiconductor device research and failure analysis. Government applications include failure analysis and characterization of advanced semiconductor fabrication processes. Commercial functions include three-dimensional material analysis for industrial, biological, and semiconductor applications. REFERENCES: 1. D. Karnakis,"Ultrafast Laser Nanomachining: Doing More With Less,"Commercial MicroManufacturing, November 2008. 2. D. Wei, S. Jacobs, S. Modla, S. Zhang, C. Young, R. Cirino, J. Caplan, and K. Czymmek,"High-resolution three-dimensional reconstruction of a whole yeast cell using focused-ion beam scanning electron microscopy,"BioTechniques 53:41-48, July 2012. 3. M. Bohr, K. Mistry,"Intel"s Revolutionary 22 nm Transistor Technology,"Intel Press Release (http://newsroom.intel.com/docs/DOC-2032#overview), May 2011. 4. International Technology Roadmap for Semiconductors, 2007 Edition, Interconnects. 5. T. Hazeldine, K. Duong,"Microsurgery for Microchips,"Materials World 10-12, November 2003 6. Information on the Defense Microelectronics Activity may be found at: http://www.dmea.osd.mil/
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