Description:
This topic is eligible for the DARPA Direct to PHASE II Pilot Program. Please see section 7.0 of the DARPA instructions for additional information. To be eligible, you must submit documentation which demonstrates that PHASE I feasibility (as described in PHASE I below). Offerors must choose between submitting a PHASE I proposal OR a Direct to PHASE II proposal, and may not submit both for the same topic. OBJECTIVE: Use measurable electronic and/or physical characteristics to identify the specific fabrication facility of origin of a given electronic component. DESCRIPTION: DARPA seeks innovative experimental and theoretical research leading to the identification of specific process signatures on an electronic component which can be uniquely associated with the semiconductor fabrication facility that manufactured the component. Current methods of identifying fab of origin are generic. These methods currently include matching observed on-chip ground rules used for polygon widths and spaces to values connected to a particular company in the literature; or finding distinctive structures or materials that are associated with specific company advertised capabilities. The Department of Defense anticipates multiple uses for such a capability, generally in the domain of improving supply chain integrity. This project seeks to find specific structural, chemical, magnetic, or electrical properties of generic on-chip features which are unique to a semiconductor fabrication facility, and which can be used as fingerprints to deterministically identify the origin of a component. Even within the same lithography node and process gate definition, certain idiosyncrasies associated with manufacturing tool installations, altitude and geomagnetic location of the facility, and chemical sources may assert detectable differences in the resulting product which can be observed or measured. Examples of facility-specific structure differences might include: specific sidewall etch angle, front-end-of line agglomeration, amount of gate activation, dose/energy/junction positioning of implants, segregation of dopants, gettering, metal line grain sizes, or wire liner thickness isotropies. Virtually thousands of characteristics and parametrics might be associated with a given chip, and indeed multiple chips and processes might be produced in a given fab simultaneously; from these, the performer will be expected to identify those parametrics that are sufficiently unique in their statistical presentation, even when compared to the same process installed in other semiconductor fabrication facilities, or across different processes. It should be assumed that these features must be recognized without the benefit of having a specific metrology or reference structures pre-placed for the purpose of identification. Analysis shall be limited to features commonly available on electronic components. While non-destructive electrical testing to determine identity provides the most utility for the application, proposals advancing destructive analysis are also acceptable. Techniques which in addition enable an estimation of the date of manufacture are encouraged. It is anticipated that in the execution of the project, a body of knowledge will be accumulated which characterizes multiple major semiconductor fabrication facilities worldwide. PHASE I: Develop a concept for identifying a semiconductor fabrication facility through the analysis of the electrical parameters of the components that are built at that facility. Through experimentation, identify the parameters, or combination of parameters, that can be used to create a measurable, repeatable signature for purposes of identification. Determine the technical feasibility of measuring the identified parameters and using those measurements to uniquely identify the manufacturing origin of an electronic component. DIRECT TO PHASE II - Offerors interested in submitting a Direct to PHASE II proposal in response to this topic must provide documentation to substantiate that the scientific and technical merit and feasibility described in the PHASE I section of this topic has been met and describes the potential commercial applications. Documentation should include all relevant information including, but not limited to: technical reports, test data, prototype designs/models, and performance goals/results. Read and follow Section 7.0 of the DARPA Instructions. PHASE II: Develop, demonstrate and validate a method for electrical and/or physical characterization of an electronic component that can be used to identify the semiconductor fabrication facility where the component was manufactured. To prove that the chosen identifying characteristics are unique to a specific manufacturing facility, validation should include the testing of parts acquired from several facilities, including testing multiple parts from each facility. The expectation is to be able to create a database of signatures which comprise the identifying characteristics for each semiconductor fabrication facility. PHASE III: Potential military applications include hardware integrity assurance, anti-tampering, threat identification, supply chain risk management and failure analysis. The ability to identify the specific fabrication facility of origin of a given electronic component has utility in a number of uses, including supply chain risk management actions, intellectual property rights and licensing enforcement, component dating and vintage analysis, and inventory control. Commercial applications include the detection of counterfeit electronic parts, establishment of intellectual property rights and licensing enforcement, supply chain risk management, hardware failure analysis and inventory control.
