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Random Number Generation for High Performance Computing

Award Information
Agency: Department of Defense
Branch: Army
Contract: W911NF-11-C-0006
Agency Tracking Number: A10A-012-0382
Amount: $99,999.00
Phase: Phase I
Program: STTR
Solicitation Topic Code: A10A-T012
Solicitation Number: 2010.A
Solicitation Year: 2010
Award Year: 2010
Award Start Date (Proposal Award Date): 2010-10-13
Award End Date (Contract End Date): 2011-04-11
Small Business Information
75 Aero Camino, Suite A
Goleta, CA 93117
United States
DUNS: 153927827
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Chris Smith
 Principal Investigator
 (978) 927-4774
Business Contact
 Rhonda Adawi
Title: Contracts Manager
Phone: (805) 685-6672
Research Institution
 University of Rhode Island
 Peter Nightingale
University of Rhode Island
Kingston, RI 2881
United States

 (401) 874-5882
 Nonprofit College or University

Frontier Technology, Inc. and University of Rhode Island Physics department propose to develop innovative, scalable random number generators for use on multiple parallel computing architectures. Our Phase I effort will include a comprehensive assessment of currently available algorithms for parallel random number generation as well as the currently available tests designed to uncover statistical defects. The considerable experience of the researchers involved in this proposal strongly suggests that the simplest and most versatile method for constructing new, more scalable algorithms will be to work with combinations of some of the most reliable generators currently available and that application based tests which rely on comparison with exactly solved models of continuous phase transitions will be among the most reliable. Random number generator algorithms and hardware specific implementations will be analyzed and optimized given the computational constraints. The most reliable and distributable of these algorithms will be implemented on multi-core systems, parallel computing clusters, graphics processing units (GPUs), GPU clusters and other parallel architectures. These algorithms will be compiled into a standardized library for release as part of a Phase II effort. A prototype of this library will be made available upon the completion of the Phase I effort.

* Information listed above is at the time of submission. *

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