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Ultra-low power"system-on-a-chip"integrated circuit for fieldable neurobiological sensing


OBJECTIVE: Develop an ultra-low voltage system for neurological sensing capable of operating with no secondary power supply, with performance in the range of current commercially available solutions. A successful application will include coordination with U.S. Army Research Laboratory (ARL) scientists to ensure understanding of the application space of sensing brain activity within real-world environments. DESCRIPTION: Recent advances in neuroscience have made great strides towards improving our understanding of how the nervous system operates and our ability to monitor its function inaction. Meanwhile, drastic improvements in sensor technology, as well as streamlined system design, have led to more wearable electroencephalography (EEG) solutions, which hold the promise of performing true neurophysiologcal monitoring outside of the lab and in more everyday or even potentially hazardous environments. For example, use of dry (gel-free) electrodes greatly minimizes preparation time, and improved higher-bandwidth wireless technology has eliminated the need for a physical tether between a wearer and the system, while also reducing artifact noise. Truly fieldable neurobiological sensing systems would be revolutionary for on-line monitoring of Soldier cognitive state in a wide range of environments, potentially integrated as part of a standard helmet or patrol cap. However, all current solutions for the electronics used within the central EEG data acquisition (DAQ) systems pose fieldability challenges because of size, weight, and power (SWAP) requirements. This is primarily due to the use of conventional integrated circuit (IC) design and components, which are based on standard operation levels of millivolts to volts and high power radios. As a result, they have an implicit requirement for conventional power supplies (e.g. batteries) that add substantial weight to the total package. Conventional systems have, at most, 8-12 hours of battery life; this adds the burden of requiring continual interaction and maintenance for the user. A system that is extremely small, lightweight, able to operate for extremely long periods (hundreds of hours to indefinitely), and requires virtually no interaction or direct attention from the user (a"construct-and-forget"approach) would reduce these barriers to fieldable systems integration and provide ground-breaking capabilities across a broad range of environments and application domains. The intended goal of this proposal is to extend the operational time per use from hours to weeks, reduce the weight of the system to a few grams, and decrease the size of the system to a couple of square centimeters, through the development and refinement of a system-on-a-chip (SoC) DAQ system targeted for external electrophysiological neurological applications (e.g. EEG), which operates on ultra-low power requirements (microwatts). While some previous work has demonstrated putative systems operating on ultra-low power [1-5], none have been produced in a usable form-factor, or that operate within a power realm low enough to be completely self-sustaining (operating in milliwatt or hundreds of microwatt range) while containing the processing requirements necessary for EEG. The Phase II goal will be to completely eliminate the necessity for an external power source through use of a local thermoelectric or other alternative source. In order to suit the largest range of envisioned applications, the final system would need to be capable of collecting high-resolution data such as from a dense array (e.g. 64+ channels), high data precision (24+ bit), or high sample rate (1 kHz) with resulting SNR comparable to that of conventional EEG measurement systems. Additionally, it must be capable of handling typical signal conditioning and pre-processing procedures for EEG, data storage, and near-field (<6 meter) transmission, with integrated power management as a central tenet. Local power may be appropriate, but must not require service/maintenance from the user, must be consistent with the goal of minimizing the size, weight, safety, and obtrusiveness of the total system, and must be compatible with long term human use applications. PHASE I: Develop a System on a Chip design with multiple channel capability (three channel minimum) for application in a dry EEG data acquisition system. The SoC should include signal conditioning, preprocessing, storage, signal transmission, and integrated power management. The overall SoC should be capable of operating on ultra-low (<100 microwatt) power supply. ARL can provide expertise in EEG application, potential use, and conventional system design as needed. Phase I deliverables include: 1) Deliver specifications and complete schematics for proposed SoC and components, 2) proof-of-principle simulation results (e.g., SPICE, CADENCE), providing evidence for operation equivalent to that of conventional-voltage EEG systems, and 3) a proposed power scavenging method that removes the need for an external power source or user maintenance, including plug-in charging or other interaction. The proposed SoC and power source should maintain an extremely small, lightweight form factor. PHASE II: Fabricate, test and validate the performance of the design developed in Phase I, and develop a generation II design with expanded channel capability and operational performance equivalent to conventional methods as evidenced in both simulated (phantom) models and human users. Coordinate with U.S. Army Research Laboratory neurotechnology experts to enable the integration and testing of the developed technologies with a full EEG system form factor in a variety of relevant environments and use conditions, which can be performed by ARL. The generation II design should expand the SoC design to potentially include high-density (64+ channel) and/or high fidelity (24 bit, 1kHz) acquisition. This could be achieved in a single SoC or by multiplexing multiple SoC chips, but must maintain the goal of operation without external power source or user maintenance. By end of performance, deliver to ARL at least 10 functional SoC chip sets either already integrated or capable of integration with systems. PHASE III: Develop a marketable device which could be used as the primary component of a fieldable EEG system, with potential uses in academic research, industry, medical, and military applications where high portability is crucial. Potential applications include monitoring of vigilance or mental fatigue, seizure prediction or identification, casualty or TBI assessment, or daily stress monitoring.
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