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Self-Reconfigurable Memristor-Based Computing Architecture: Design, Fabrication, and Characterization

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA8750-13-C-0023
Agency Tracking Number: F10B-T31-0192
Amount: $748,070.00
Phase: Phase II
Program: STTR
Solicitation Topic Code: AF10-BT31
Solicitation Number: 2010.B
Solicitation Year: 2010
Award Year: 2013
Award Start Date (Proposal Award Date): 2012-11-08
Award End Date (Contract End Date): 2014-11-07
Small Business Information
2106 Manitou Ave
Boise, ID 83706-4151
United States
DUNS: 963322271
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Terry Gafron
 Officer, PI Engineer
 (208) 585-8465
Business Contact
 Jennifer Regner
Title: Officer, Operations Manager
Phone: (208) 859-2835
Research Institution
 Boise State University
 Karen Henry
1910 University Drive
Boise, ID 83725-
United States

 (208) 426-4420
 Nonprofit college or university

ABSTRACT: The chalcogenide based ion-conducting memristor has been shown to be an effective element as the core of a simple neuromorphic computing circuit. The response of the computing circuit is the result of weighted external stimuli, the current state of the device, and the history of exposure by the device to the stimuli. A highly specialized version of the device, as developed by the Advanced Memory and Reconfigurable Logic Group at Boise State University led by Dr. Kris Campbell, PhD. will be designed, fabricated, and integrated to form the core of a"plug and play"soft processor microchip. Leveraging the unique properties of the memristor device, the soft processor will exploit the nature-like learning capabilities of a memristor based synthetic synapse to form an adaptive, responsive, rudimentary learning system on a chip. The synapses, fabricated to form an addressable neural fabric will be fully integrated into conventional digital support architectures, including standard buffers, registers, a communications BUS, and input/output ports. Device design and fabrication will be developed using industry standard tools and well established technology nodes, enabling quick and effective integration into the mainstream electronics community, providing opportunities for unprecedented advances in intelligent computing architectures, adaptive analysis, and responsive control systems. BENEFIT: The primary technical objective of the Phase II work is the design and fabrication of a fully functional Plug-and-Play"soft processor"chip based on the chalcogenide ion-conducting thin film memristor tested in the Phase I effort. The commercial target is straightforward: develop a"soft processor"designed using chalcogenide based ion-conducting thin film memristors, operating as a hardware based, high speed neural network, capable of fuzzy logic decision and classification of input signals. The design and fabrication is intended to be fully industry compatible, utilizing industry recognized tools, technology nodes, and methodologies. The final component is intended to be easily integrated into commercial circuit designs. The objective is to provide the electronics industry with a self-contained functional memristor based building block that can be applied by any designer with reasonable skills and design tools. The expectation is that the building block chip enabled by this Phase II work will enable a large variety of engineers and scientists to develop applications currently unimagined with existing technology limitations.

* Information listed above is at the time of submission. *

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