You are here

Radiation Fault Analysis for 45 Nanometer CMOS-SOI VLSI Circuits

Award Information
Agency: Department of Defense
Branch: Defense Threat Reduction Agency
Contract: HDTRA1-10-P-0023
Agency Tracking Number: T092-001-0041
Amount: $99,836.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: DTRA092-001
Solicitation Number: 2009.2
Timeline
Solicitation Year: 2009
Award Year: 2010
Award Start Date (Proposal Award Date): 2010-02-18
Award End Date (Contract End Date): 2010-08-17
Small Business Information
P. O. Box 19325
Portland, OR 97280
United States
DUNS: 142981153
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 James Holmes
 Vice President
 (479) 575-9222
 holmes@lynguent.com
Business Contact
 Barbara Bakken
Title: Chief Operations Officer
Phone: (503) 241-7195
Email: bbakken@lynguent.com
Research Institution
N/A
Abstract

State of the art Radiation Hardened by Design (RHBD) techniques must scale down in feature size for radiation effects in 45 nm processes, and also scale up in complexity to support radiation fault analysis of VLSI circuits. Recent access to commercial 45 nm CMOS Silicon-on-Insulator (SOI) technologies has increased the interest in this technology for rad-hard electronic applications due to the inherent advantages for operation in radiation environments. However, the models that exist in the commercial design environments do not include the effects of radiation. Lynguent’s efficiency gains in compact model composition have enabled Vanderbilt-ISDE to transfer observed radiation effects from TCAD simulators into the commercial circuit simulators and correlate the results with measured data at the 90 nm process node. Applying Lynguent’s tools to a 45 nm CMOS SOI PDK is the logical next step in establishing radiation awareness at 45 nm. The outcome of this Phase 1 effort will be a fully featured BSIMSOI-CMX model and the definition of 45 nm Radiation Effects Library for use in the ModLyngTM Integrated Modeling Environment (IME). These Phase 1 results provide the platform for a Phase 2 implementation of high fidelity radiation fault analysis on 45 nm VLSI circuits and libraries.

* Information listed above is at the time of submission. *

US Flag An Official Website of the United States Government